Method of fabricating integrated fan-out packages
A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.
1. A method, comprising:
forming a redistribution circuit structure on an integrated circuit component laterally encapsulated by an insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the integrated circuit component, and forming the redistribution circuit structure comprising:
forming a first conductive via on the integrated circuit component;
forming a first dielectric layer on the integrated circuit component and the insulating encapsulation to cover the first conductive via, wherein top surfaces of the first conductive via and the first dielectric layer are higher than a top surface of the insulating encapsulation;
performing a first polishing process to polish the first dielectric layer to expose a top surface of the first conductive via such that a first level height offset is present between the top surface of the first conductive via and a top surface of the first dielectric layer after performing the first polishing process;
forming a first seed layer and a first redistribution wiring over the first conductive via, the first seed layer being in contact with a portion of the first dielectric layer;
forming a second conductive via on the first redistribution wiring;
forming a second dielectric layer on the first dielectric layer to cover the second conductive via and the first redistribution wiring; and
performing a second polishing process to polish the second dielectric layer to expose a top surface of the second conductive via such that a second level height offset is present between the top surface of the second conductive vias and a top surface of the second dielectric layer.
2. The method as claimed in claim 1 further comprising:
forming a second seed layer and a second redistribution wiring over the second conductive via, the second seed layer being in contact with a portion of the second dielectric layer.
3. The method as claimed in claim 2 further comprising:
forming a third dielectric layer on the second dielectric layer;
forming a third via opening in the third dielectric layer, the third via opening exposing the second redistribution wiring; and
forming a third redistribution wiring on the third dielectric layer, the third being electrically connected to the second redistribution wiring through the third via opening in the third dielectric layer.
4. The method as claimed in claim 3 further comprising:
forming a fourth dielectric layer on the third dielectric layer;
forming a fourth via opening in the fourth dielectric layer, the fourth via opening exposing the third redistribution wiring; and
forming a pad on the fourth dielectric layer, the pad being electrically connected to the third redistribution wiring through the fourth via opening in the fourth dielectric layer.
5. The method as claimed in claim 1 , wherein a first polishing rate of the first conductive vias is greater than a second polishing rate of the first dielectric layer when performing the first polishing process.
6. The method as claimed in claim 1 , wherein a first polishing rate of the first conductive vias is less than a second polishing rate of the first dielectric layer when performing the first polishing process.
7. The method as claimed in claim 1 , wherein a third polishing rate of the second conductive vias is greater than a fourth polishing rate of the second dielectric layer when performing the second polishing process.
8. The method as claimed in claim 1 , wherein a third polishing rate of the second conductive vias is less than a fourth polishing rate of the second dielectric layer when performing the second polishing process.
9. The method as claimed in claim 1 , wherein the first polishing process or the second polishing process comprises chemical mechanical polishing.
10. A method, comprising:
forming a redistribution circuit structure on an integrated circuit component laterally encapsulated by an insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the integrated circuit component, and forming the redistribution circuit structure comprising:
forming a first conductive via on the integrated circuit component;
forming a first dielectric layer on the integrated circuit component and the insulating encapsulation to cover the first conductive via;
performing a first polishing process to polish the first dielectric layer until the first conductive via is exposed, wherein a sidewall of the first conductive via or a sidewall of the first dielectric layer is exposed after performing the first polishing process;
forming a first seed layer and a first redistribution wiring on the first conductive via and a portion of the first dielectric layer, wherein the sidewall of the first conductive via or the sidewall of the first dielectric layer is covered by the first seed layer;
forming a second conductive via on the first redistribution wiring;
forming a second dielectric layer on the first dielectric layer to cover the second conductive via and the first redistribution wiring; and
performing a second polishing process to polish the second dielectric layer until the second conductive via is exposed.
11. The method as claimed in claim 10 further comprising:
forming a second seed layer and a second redistribution wiring on the second conductive via, the second seed layer being in contact with a portion of the second dielectric layer.
12. The method as claimed in claim 11 further comprising:
forming a third dielectric layer on the second dielectric layer;
forming a third via opening in the third dielectric layer, the third via opening exposing the second redistribution wiring; and
forming a third redistribution wiring on the third dielectric layer, the third being electrically connected to the second redistribution wiring through the third via opening in the third dielectric layer.
13. The method as claimed in claim 12 further comprising:
forming a fourth dielectric layer on the third dielectric layer;
forming a fourth via opening in the fourth dielectric layer, the fourth via opening exposing the third redistribution wiring; and
forming a pad on the fourth dielectric layer, the pad being electrically connected to the third redistribution wiring through the fourth via opening in the fourth dielectric layer.
14. The method as claimed in claim 10 , wherein a first polishing rate of the first conductive vias is greater than a second polishing rate of the first dielectric layer when performing the first polishing process, and the exposed top surface of the first conductive via is lower than the exposed top surface of the first dielectric layer.
15. The method as claimed in claim 10 , wherein a first polishing rate of the first conductive vias is less than a second polishing rate of the first dielectric layer when performing the first polishing process, and the exposed top surface of the first conductive via is higher than the exposed top surface of the first dielectric layer.
16. The method as claimed in claim 10 , wherein a third polishing rate of the second conductive vias is greater than a fourth polishing rate of the second dielectric layer when performing the second polishing process, and the exposed top surface of the second conductive via is lower than the exposed top surface of the second dielectric layer.
17. The method as claimed in claim 10 , wherein a third polishing rate of the second conductive vias is less than a fourth polishing rate of the second dielectric layer when performing the second polishing process, and the exposed top surface of the second conductive via is higher than the exposed top surface of the second dielectric layer.
18. A method, comprising:
forming a redistribution circuit structure on an integrated circuit component laterally encapsulated by an insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the integrated circuit component, and forming the redistribution circuit structure comprising:
forming a first conductive via on the integrated circuit component;
forming a first dielectric layer on the integrated circuit component and the insulating encapsulation to cover the first conductive via;
performing a first polishing process to polish the first dielectric layer until a first level height offset is present between exposed top surfaces of the first conductive via and the first dielectric layer; and
forming a first seed layer and a first redistribution wiring over the first conductive via, the first seed layer being in contact with a portion of the first dielectric layer.
19. The method as claimed in claim 18 , wherein the exposed top surface of the first conductive via is higher than the exposed top surface of the first dielectric layer after performing a first polishing process.
20. The method as claimed in claim 18 , wherein the exposed top surface of the first conductive via is lower than the exposed top surface of the first dielectric layer after performing a first polishing process.