Apparatuses and methods for operations in a self-refresh state

1. A system, comprising:

a memory device; and

a host configured to operate in a first power mode in which commands are provided to the memory device and a second power mode in which commands are not provided to the memory device;

wherein the memory device is configured to:

enter a self-refresh state responsive to the host entering the second power mode; and

while in the self-refresh state, operate in a selected one of a plurality of modes, wherein the plurality of modes includes:

a first mode in which the memory device is configured to perform compute operations on data stored in an array of the memory device; and

a second mode in which the memory device is configured to not perform compute operations on data stored in the array.

2. The system of claim 1 , wherein the second power state is a low power state in which no data or commands are transferred between the host and the memory device.

3. The system of claim 1 , wherein the memory device includes a mode register configured to provide the plurality of modes.

4. The system of claim 1 , wherein the memory device is configured to, while in the self-refresh state and operating in the first mode, perform compute operations on data stored in the array to perform facial detection in image data, or feature extraction from image data, or both.

5. The system of claim 1 , wherein the memory device is configured to, while in the self-refresh state and operating in the first mode, perform compute operations on data stored in the array to perform a security scan of in-memory threats.

6. The system of claim 1 , wherein the memory device is configured to, while in the self-refresh state and operating in the first mode, perform compute operations on data stored in the array to perform neural network processing.

7. The system of claim 1 , wherein the memory device is configured to, while in the self-refresh state and operating in the first mode, perform compute operations on data stored in the array at a slower rate than a rate at which the memory device is configured to perform compute operations when not in the self-refresh state.

8. The system of claim 7 , wherein the slower rate corresponds to a default refresh rate used to refresh the array when the memory device is in the self-refresh state.

9. The system of claim 1 , wherein the memory device is a processing in memory device comprising control circuitry configured to direct performance of compute operations on data stored in the array when the memory device is in the self-refresh state and when the memory device is in a state other than the self-refresh state.

10. The system of claim 1 , wherein the system is a battery-powered mobile device.

11. The system of claim 1 , wherein the memory device comprises:

sensing circuitry coupled to the array and comprising a plurality of compute components; and

control circuitry configured to operate the plurality of compute components as respective one bit processing elements in association with performing compute operations on data stored in the array.

12. An apparatus, comprising:

an array of memory cells coupled to sensing circuitry; and

control circuitry coupled to the array and configured to:

receive commands from a host when the host is operating in a first power mode;

operate in a self-refresh state responsive to the host entering a second power mode in which commands are not received from the host;

while operating in the self-refresh state, operate in a selected one of a plurality of modes, wherein the plurality of modes includes:

a first mode in which the control circuitry is configured to control performance of compute operations on data stored in the array; and

a second mode in which the control circuitry is configured to not perform compute operations on data stored in the array.

13. The apparatus of claim 12 , wherein the apparatus comprises a battery-powered mobile device in which the host is coupled to a memory device, wherein the memory devices comprises:

the array of memory cells;

the control circuitry; and

a mode register configured to be set by the host to indicate the selected one of the plurality of modes.

14. The apparatus of claim 13 , wherein the compute operations performed while the control circuitry is operating in the self-refresh state and in accordance with the first mode, are performed to process data to be later accessed by the host subsequent to the host returning from the second power mode to the first power mode.

15. The apparatus of claim 12 , wherein the plurality of modes includes a third mode in which the control circuitry is configured to control performance of compute operations on data stored in the array at a different rate than a rate corresponding to the first mode.

16. The apparatus of claim 15 , wherein the rate corresponding to the first mode is aligned with a default frequency for a memory refresh cycle corresponding to the self-refresh state.

17. The apparatus of claim 12 , wherein the control circuitry is configured to, while operating in the first mode corresponding to the self-refresh state, control processing of image data stored in the array via the compute operations.

18. A system, comprising:

a processing in memory device; and

a host configured to operate in a power mode in which commands are provided to the processing in memory device and a low power mode in which commands are not provided to the processing in memory device;

wherein the processing in memory device is configured to:

enter a self-refresh state responsive to the host entering the low power mode, wherein a default frequency for a refresh cycle corresponding to the self-refresh state is different than a frequency for a refresh cycle corresponding to a non-self-refresh state;

while in the self-refresh state and commands are not being provided to the processing in memory device from the host, perform a background operation that does not involve interaction with the host; and

responsive to the host exiting the self-refresh state, provide a result of the background operation to the host.

19. The system of claim 18 , wherein the background operation is an operation selected from the group comprising:

a facial detection in images operation;

a feature extraction in images operation;

security scan of in-memory threats operation; and

a neural network processing operation.

20. The system of claim 18 , wherein the processing in memory device includes a mode register configured to be set, by the host, to indicate the selected one of the plurality of modes, and wherein the plurality of modes includes:

a second mode in which the processing in memory device is configured to not execute compute operations on data stored in the array; and

a third mode in which the processing in memory device is configured to execute the compute operations on the data stored in the array at a rate that is different than a rate at which the compute operations are executed when the processing in memory device is in the first mode.