Semiconductor package and method of manufacturing same

1. A semiconductor package, comprising:

a first redistribution structure including first redistribution conductors;

a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors;

a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors;

an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor;

a barrier layer extending along an upper surface of the encapsulant; and

a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.

2. The semiconductor package of claim 1 , wherein the encapsulant covers an upper surface of the semiconductor chip and at least a portion of an upper surface of the connection conductor, and

the second redistribution conductor penetrates through the barrier layer and the encapsulant.

3. The semiconductor package of claim 1 , wherein the barrier layer includes nickel, and the second redistribution conductor includes copper.

4. The semiconductor package of claim 1 , wherein the encapsulant includes an insulating material including an inorganic filler.

5. The semiconductor package of claim 1 , wherein the barrier layer is not in contact with the connection conductor.

6. The semiconductor package of claim 1 , further comprising:

a solder resist layer on the encapsulant, covering the second redistribution conductor and including an opening exposing at least a portion of the second redistribution conductor.

7. The semiconductor package of claim 6 , further comprising:

a surface metal layer on the at least a portion of the second redistribution conductor exposed through the opening.

8. The semiconductor package of claim 7 , wherein the surface metal layer includes nickel.

9. A semiconductor package comprising:

a first redistribution structure including first redistribution conductors;

a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors;

a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connecting the first redistribution conductors;

an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor;

a barrier layer on the encapsulant; and

a second redistribution conductor electrically connected to the first redistribution conductor through the connection conductor and including a pattern portion on the barrier layer, and a via portion penetrating through the barrier layer and extending from the pattern portion towards the connection conductor.

10. The semiconductor package of claim 9 , wherein the second redistribution conductor includes a seed layer and a plating layer on the seed layer,

the plating layer includes the pattern portion and the via portion, and

the seed layer extends along a lower surface of the pattern portion and a side surface and a lower surface of the via portion.

11. The semiconductor package of claim 10 , wherein the seed layer is separated from an upper surface of the encapsulant by the barrier layer.

12. The semiconductor package of claim 10 , wherein the via portion is disposed in a through-hole penetrating the barrier layer and a portion of the encapsulant to expose at least a portion of the connection conductor, and

the seed layer directly contacts the encapsulant in the through-hole.

13. The semiconductor package of claim 10 , wherein each of the seed layer and the plating layer includes copper, and the barrier layer includes nickel.

14. The semiconductor package of claim 10 , wherein a thickness of the seed layer is about 1 μm or less.

15. The semiconductor package of claim 9 , wherein the barrier layer has a thickness of about 1 μm or less.

16. The semiconductor package of claim 9 , wherein a side surface of the barrier layer has a step difference with respect to a side surface of the pattern portion.

17. The semiconductor package of claim 9 , further comprising:

an insulating layer between the encapsulant and the barrier layer, wherein the via portion penetrates the insulating layer and a portion of the encapsulant covering an upper surface of the connection conductor.

18. A semiconductor package comprising:

a first redistribution structure including first redistribution conductors;

a semiconductor chip on the first redistribution structure and including connection pads electrically connected to the first redistribution conductors;

a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and including a first seed layer and a first plating layer on the first seed layer;

an encapsulant sealing the semiconductor chip and at least a portion of the connection conductor;

a barrier layer extending along an upper surface of the encapsulant; and

a second redistribution conductor on the barrier layer, penetrating through the barrier layer to contact the connection conductor, and including a second seed layer and a second plating layer on the second seed layer.

19. The semiconductor package of claim 18 , wherein the second seed layer has a thickness less than a thickness of the first seed layer.

20. The semiconductor package of claim 18 , wherein a combination of the barrier layer and the second seed layer has a thickness of about 0.6 μm or less.