Link initialization training and bring up for die-to-die interconnect
In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.
1. An apparatus comprising:
a first die comprising:
a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, wherein the die-to-die adapter is to receive message information, the message information comprising first information of a first interconnect protocol; and
the physical layer circuitry coupled to the die-to-die adapter, wherein the physical layer circuitry is to receive and output the first information to a second die via an interconnect, and wherein the physical layer circuitry is further to apply a lane reversal to at least some of a plurality of transmit data lanes of the first die in response to a detection of a reversal between receive data lanes of the first die and corresponding transmit data lanes of the second die;
wherein the physical layer circuitry, after a reset flow for the first die, is to:
perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die;
after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and
after the mainband initialization, perform a mainband training of the mainband interface at a negotiated data rate.
2. The apparatus of claim 1 , wherein the die-to-die adapter, after the mainband training, is to perform a link initialization to exchange adapter and link management messages.
3. The apparatus of claim 2 , wherein after the link initialization, the physical layer circuitry is to be enabled to perform protocol flit transfers via the mainband interface.
4. The apparatus of claim 1 , wherein the mainband initialization comprises a lane reversal detection to detect whether at least some of a plurality of receive data lanes associated with the first die are reversed with respect to corresponding transmit data lanes associated with the second die.
5. The apparatus of claim 4 , wherein the lane reversal detection comprises to send a lane reversal detection pattern on a plurality of transmit data lanes associated with the first die and receive the lane reversal detection pattern on the plurality of receive data lanes associated with the first die.
6. The apparatus of claim 5 , wherein in response to detection of the lane reversal, the physical layer circuitry is to reverse a logical lane order of at least some of the plurality of transmit data lanes.
7. The apparatus of claim 1 , wherein the mainband initialization comprises a lane error detection to detect whether an error is present in a first receive data lane associated with the first die, and in response to detection of the error, to repair the error via a redundant receive data lane associated with the first die.
8. The apparatus of claim 1 , further comprising a package comprising the first die and the second die, wherein the interconnect comprises an on-package interconnect to couple the first die and the second die.
9. The apparatus of claim 8 , further comprising a package substrate, the package substrate comprising the on-package interconnect adapted within a silicon bridge.
10. The apparatus of claim 8 , further comprising an interposer, the interposer comprising the on-package interconnect.
11. The apparatus of claim 1 , wherein the interconnect comprises a multi-protocol capable interconnect having a Universal Chiplet Interconnect express (UCIe) architecture, the first interconnect protocol comprising a flit mode of a Peripheral Component Interconnect express (PCIe) protocol and the interconnect further to communicate second information of a second interconnect protocol, the second interconnect protocol comprising a flit mode of a Compute Express Link (CXL) protocol.
12. A method comprising:
receiving, in a plurality of receive data lanes associated with a first die of a package comprising the first die and a second die, a lane reversal detect pattern from the second die, each of the plurality of receive data lanes to receive the lane reversal detect pattern having a different lane identifier;
determining whether at least some of the plurality of receive data lanes associated with the first die are reversed with respect to corresponding ones of a plurality of transmit data lanes associated with the second die based at least in part on the lane reversal detect pattern; and
in response to a determination that the at least some of the plurality of receive data lanes associated with the first die are reversed with respect to the corresponding ones of the plurality of transmit data lanes associated with the second die, applying a lane reversal to at least some of a plurality of transmit data lanes associated with the first die.
13. The method of claim 12 , further comprising receiving the lane reversal detect pattern comprising a predetermined pattern and the different lane identifier.
14. The method of claim 12 , further comprising receiving the lane reversal detect pattern comprising 16 bits and receiving the different lane identifier comprising 8 bits.
15. The method of claim 12 , further comprising:
for each of a plurality of iterations of receiving the lane reversal detect pattern:
determining, for each of the plurality of receive data lanes, whether the different lane identifier of the lane reversal detect pattern matches a lane identifier of the receive data lane; and
in response to a match, updating a valid count.
16. The method of claim 15 , further comprising determining that the at least some of the plurality of receive data lanes associated with the first die are reversed in response to at least a threshold number of the plurality of receive data lanes having the valid count less than a threshold valid count.
17. A package comprising:
a first die comprising a central processing unit (CPU) and a protocol stack comprising:
a die-to-die adapter to communicate with a protocol layer via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to communicate message information, the message information comprising first information of a first interconnect protocol; and
the physical layer circuitry coupled to the die-to-die adapter, wherein the physical layer circuitry is to receive and output the first information to a second die via an interconnect,
wherein the physical layer circuitry comprises:
clock circuitry to send a clock signal;
data valid circuitry to send a data valid signal; and
data transmitter circuitry to send data via a plurality of data lanes, wherein in response to detection of a lane reversal, the physical layer circuitry is to reverse a logical lane order of at least some of the plurality of data lanes; and
the second die coupled to the first die via the interconnect.
18. The package of claim 17 , wherein the plurality of data lanes comprises a redundant data lane, wherein in response to detection of a fault in a first data lane, the physical layer circuitry is to remap the first data lane to the redundant data lane.
19. The package of claim 17 , wherein the physical layer circuitry is to detect the lane reversal based at least in part on receipt of a lane reversal detect pattern comprising a predetermined pattern and a lane identifier.
20. The package of claim 17 , wherein the second die comprises an accelerator, wherein the first die is to communicate with the second die according to at least one of a flit mode of a Peripheral Component Interconnect express (PCIe) protocol or a flit mode of a Compute Express Link (CXL) protocol.