Standard interfaces for die to die (D2D) interconnect stacks
In one embodiment, a first die comprises: a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), where the first die-to-die adapter is to receive message information comprising first information of a first interconnect protocol; and the first physical layer circuitry coupled to the first die-to-die adapter. The first physical layer circuitry may be configured to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry. Other embodiments are described and claimed.
1 . An apparatus comprising:
a first die comprising:
a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), wherein the first die-to-die adapter is to receive message information, the message information comprising first information of a first interconnect protocol; and
the first physical layer circuitry coupled to the first die-to-die adapter, wherein the first physical layer circuitry is to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry;
wherein the interconnect comprises a mainband and a sideband;
wherein the first die-to-die adapter is to send a first signal having a set state to the first protocol layer circuitry via the FDI to indicate completion of link training of the interconnect;
wherein the first die-to-die adapter is to perform a wake request handshake with the first protocol layer circuitry via the FDI; and
wherein after the wake request handshake, the first die-to-die adapter is to send a first sideband message to the second die via the sideband to indicate that the first protocol layer circuitry is in an active state.
2 . The apparatus of claim 1 , wherein the first die-to-die adapter is to host a plurality of protocol layer circuitries, wherein the first die-to-die adapter is to couple with the first protocol layer circuitry via a first FDI and couple with second protocol layer circuitry via a second FDI.
3 . The apparatus of claim 2 , wherein the first die-to-die adapter is to maintain a first independent state machine for the first protocol layer circuitry and a second independent state machine for the second protocol layer circuitry.
4 . The apparatus of claim 2 , wherein the first die-to-die adapter further comprises a stack multiplexer, wherein the stack multiplexer is to receive the first information from the first protocol layer circuitry and receive second information from the second protocol layer circuitry and to pass at least one of the first information or the second information to the first physical layer circuitry via the RDI.
5 . The apparatus of claim 4 , further comprising a plurality of arbiters/multiplexers, the plurality of arbiters/multiplexers coupled to the stack multiplexer.
6 . The apparatus of claim 4 , wherein the first die-to-die adapter further comprises an arbiter/multiplexer to receive Compute Express Link (CXL) memory (CXL.mem) information of a second interconnect protocol and CXL input/output (CXL.i/o) information of the second interconnect protocol.
7 . The apparatus of claim 1 , wherein the first die-to-die adapter is to send to the first physical layer circuitry at least one of cyclic redundancy checksum (CRC) information or parity information staggered with respect to data associated with the CRC information or the parity information.
8 . The apparatus of claim 1 , wherein the first physical layer circuitry is to send an inband presence state signal having a reset state after a reset of the first die and prior to sideband training.
9 . The apparatus of claim 8 , wherein after the sideband training and mainband training, the first physical layer circuitry is to send the inband presence state signal having a set state.
10 . The apparatus of claim 9 , wherein the first die-to-die adapter is to be in a clock gated state until receipt of the inband presence state signal having the set state.
11 . The apparatus of claim 1 , wherein the interconnect comprises a multi-protocol capable interconnect having a Universal Chiplet Interconnect express (UCIe) architecture, the first interconnect protocol comprising a flit mode of a Peripheral Component Interconnect express (PCIe) protocol and the interconnect further to communicate second information of a second interconnect protocol, the second interconnect protocol comprising a flit mode of a Compute Express Link (CXL) protocol.
12 . A method comprising:
performing, via physical layer circuitry of a first die, a link training of a mainband of an interconnect coupling the first die with a second die, the interconnect comprising the mainband and a sideband;
after performing the link training, sending a first signal having a set state to a die-to die adapter of the first die coupled to the physical layer circuitry via a raw die-to-die interface (RDI), the first signal having the set state to indicate completion of the link training;
performing a wake request handshake with the die-to-die adapter via the RDI; and
after the wake request handshake, sending a first sideband message to the second die via the sideband to indicate that the die-to-die adapter is in an active state.
13 . The method of claim 12 , further comprising performing a first request handshake with the die-to-die adapter to request removal of clock gating.
14 . The method of claim 12 , further comprising:
receiving a second sideband message from the second die via the sideband, the second sideband message to indicate that a die-to-die adapter of the second die is in an active state; and
sending a third sideband message to the second die via the sideband, the third sideband message to acknowledge the second sideband message.
15 . The method of claim 12 , further comprising performing a symmetric power management flow between the physical layer circuitry and second physical layer circuitry of the second die, and thereafter transitioning the physical layer circuitry to a power savings state.
16 . A package comprising:
a first die comprising a central processing unit (CPU) and a protocol stack comprising:
a die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to communicate message information, the message information comprising first information of a first interconnect protocol; and
the physical layer circuitry coupled to the die-to-die adapter via the RDI, wherein the physical layer circuitry is to receive and output the first information to a second die via an interconnect comprising a mainband and a sideband;
wherein the die-to-die adapter is to:
send a first signal having a set state to the protocol layer circuitry via the FDI to indicate completion of link training of the interconnect;
perform a wake request handshake with the protocol layer circuitry via the FDI; and
after the wake request handshake, send a first sideband message to the second die via the sideband to indicate that the protocol layer circuitry is in an active state; and the second die coupled to the first die via the interconnect.
17 . The package of claim 16 , wherein the die-to-die adapter, in response to an adapter active request sideband message from the second die, is to ensure that a receiver of the protocol layer circuitry is in an active state and then send an adapter active response sideband message to the second die.
18 . The package of claim 16 , wherein the physical layer circuitry is to perform a sideband initialization of the sideband after a reset flow for the first die that is independent of a reset flow for the second die.
19 . The package of claim 16 , further comprising a package substrate, the package substrate comprising the interconnect, the interconnect comprising an on-package interconnect to couple the first die and the second die.
20 . The package of claim 16 , wherein the second die comprises an accelerator, wherein the first die is to communicate with the second die according to at least one of a flit mode of a Peripheral Component Interconnect express (PCIe) protocol or a flit mode of a Compute Express Link (CXL) protocol.