Memory cell design
View Patent ↗Memory devices are provided. A memory device according to the present disclosure includes a first pull-down device (PD-1), a second pull-down device (PD-2), a first pass-gate device (PG-1), and a second pass-gate device (PG-2) disposed in a first p-well on a substrate, and a first pull-up device (PU-1), a second pull-up device (PU-2), a first isolation device (IS-1), and a second isolation device (IS-2) disposed in an n-well adjacent the first p-well. The PD-1, the PD-2, the PG-1, and the PG-2 share a first active region. The PU-1, the PU-2, the IS-1, and the IS-2 share a second active region. A first gate of the IS-1 and a second gate of the IS-2 are coupled to a positive supply voltage. A drain of the PU-1 and a drain of the PU-2 are coupled to the positive supply voltage (CVdd).
1. A memory device, comprising:
a first pull-down device (PD-1), a second pull-down device (PD-2), a first pass-gate device (PG-1), and a second pass-gate device (PG-2) disposed in a first p-well on a substrate;
a first pull-up device (PU-1), a second pull-up device (PU-2), a first isolation device (IS-1), and a second isolation device (IS-2) disposed in an n-well adjacent the first p-well; and
a metal line extending over the n-well,
wherein the first pull-down device (PD-1), the second pull-down device (PD-2), the first pass-gate device (PG-1), and the second pass-gate device (PG-2) share a first active region,
wherein the first pull-up device (PU-1), the second pull-up device (PU-2), the first isolation device (IS-1), and the second isolation device (IS-2) share a second active region,
wherein the metal line continuously spans over and is electrically coupled to a first gate of the first isolation device (IS-1) and a second gate of the second isolation device (IS-2),
wherein the metal line is coupled to a positive supply voltage,
wherein a drain of the first pull-up device (PU-1) and a drain of the second pull-up device (PU-2) are coupled to the positive supply voltage (CVdd).
2. The memory device of claim 1 ,
wherein the first active region and the second active region extend lengthwise along a first direction,
wherein a length of the first active region along the first direction is the same as a length of the second active region along the first direction.
3. The memory device of claim 2 ,
wherein the first active region comprises a plurality of fins,
wherein the second active region comprises a single fin.
4. The memory device of claim 2 ,
wherein the first active region comprises a first vertical stack of nanostructures,
wherein the second active region comprises a second vertical stack of nanostructures,
wherein each of the first vertical stack of nanostructures comprises a first width along a second direction perpendicular to the first direction,
wherein each of the second vertical stack of nanostructures comprises a second width along the second direction,
wherein the first width is greater than the second width.
5. The memory device of claim 1 , further comprising:
a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third pass-gate device (PG-3), and a fourth pass-gate device (PG-4) disposed in a second p-well on the substrate, the n-well being sandwiched between the first p-well and the second p-well; and
a third pull-up device (PU-3), a fourth pull-up device (PU-3), a third isolation device (IS-3), and a fourth isolation device (IS-4) disposed in the n-well,
wherein the third pull-down device (PD-3), the fourth pull-down device (PD-4), the third pass-gate device (PG-3), and the fourth pass-gate device (PG-4) share a third active region,
wherein the third pull-up device (PU-3), the fourth pull-up device (PU-3), the third isolation device (IS-3), and the fourth isolation device (IS-4) share a fourth active region,
where a gate of the third isolation device (IS-3) and a gate of the fourth isolation device (IS-4) are coupled to the positive supply voltage (CVdd).
6. The memory device of claim 5 ,
wherein the first isolation device (IS-1) and the third isolation device (IS-3) share the first gate,
wherein the second isolation device (IS-2) and the fourth isolation device (IS-4) share the second gate.
7. The memory device of claim 6 ,
wherein the first gate is electrically coupled to the metal line by way of a first via,
wherein the second gate is electrically coupled to the metal line by way of a second via.
8. A memory structure, comprising:
a first cell structure comprising:
a first pull-down device (PD-1), a second pull-down device (PD-2), a first pass-gate device (PG-1), and a second pass-gate device (PG-2) disposed in a first p-well on a substrate, and
a first pull-up device (PU-1), a second pull-up device (PU-2), a first isolation device (IS-1), and a second isolation device (IS-2) disposed in an n-well adjacent the first p-well; and
a second cell structure comprising:
a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third pass-gate device (PG-3), and a fourth pass-gate device (PG-4) disposed in a second p-well such that the n-well is sandwiched between the first p-well and the second p-well, and
a third pull-up device (PU-3), a fourth pull-up device (PU-4), a third isolation device (IS-3), and a fourth isolation device (IS-4) disposed in the n-well,
wherein the first isolation device (IS-1) and the third isolation device (IS-3) share a first gate,
wherein the second isolation device (IS-2) and the fourth isolation device (IS-4) share a second gate,
wherein the first gate and the second gate are electrically coupled to a positive supply voltage (CVdd).
9. The memory structure of claim 8 , wherein the second cell structure is a mirror image to the first cell structure with respect to a center line of the n-well.
10. The memory structure of claim 9 , further comprising:
a first metal line electrically coupled to the positive supply voltage (CVdd),
wherein the first gate is electrically coupled to the first metal line by way of a first via,
wherein the second gate is electrically coupled to the first metal line by way of a second via,
wherein the first metal line is disposed directly over the center line.
11. The memory structure of claim 8 ,
wherein the first pull-down device (PD-1), the second pull-down device (PD-2), the first pass-gate device (PG-1), and the second pass-gate device (PG-2) share a first active region extending lengthwise along a first direction,
wherein the first pull-up device (PU-1), the second pull-up device (PU-2), the first isolation device (IS-1), and the second isolation device (IS-2) share a second active region extending lengthwise along the first direction,
wherein the third pull-up device (PU-3), the fourth pull-up device (PU-4), the third isolation device (IS-3), and the fourth isolation device (IS-4) share a third active region extending lengthwise along the first direction,
wherein the third pull-down device (PD-3), the fourth pull-down device (PD-4), the third pass-gate device (PG-3), and the fourth pass-gate device (PG-4) share a fourth active region extending lengthwise along the first direction.
12. The memory structure of claim 11 , wherein lengths of the first active region, the second active region, the third active region, and the fourth active region along the first direction are the same.
13. The memory structure of claim 12 ,
wherein the first active region comprises a first plurality of fins,
wherein the second active region comprises a first single fin,
wherein the third active region comprises a second single fin,
wherein the fourth active region comprises a second plurality of fins.
14. The memory structure of claim 13 , wherein each of the first plurality of fins and the second plurality of fins comprises two semiconductor fins.
15. The memory structure of claim 11 ,
wherein the first active region comprises a first vertical stack of nanostructures,
wherein the second active region comprises a second vertical stack of nanostructures,
wherein each of the first vertical stack of nanostructures comprises a first width along a second direction perpendicular to the first direction,
wherein each of the second vertical stack of nanostructures comprises a second width along the second direction,
wherein the first width is greater than the second width.
16. A memory structure, comprising:
a first cell structure comprising:
a first pull-down device (PD-1), a second pull-down device (PD-2), a first pass-gate device (PG-1), and a second pass-gate device (PG-2) sharing a first active region extending lengthwise along a first direction, and
a first pull-up device (PU-1), a second pull-up device (PU-2), a first isolation device (IS-1), and a second isolation device (IS-2) sharing a second active region extending lengthwise along the first direction; and
a second cell structure comprising:
a third pull-down device (PD-3), a fourth pull-down device (PD-4), a third pass-gate device (PG-3), and a fourth pass-gate device (PG-4) sharing a third active region extending lengthwise along the first direction, and
a third pull-up device (PU-3), a fourth pull-up device (PU-4), a third isolation device (IS-3), and a fourth isolation device (IS-4) sharing a fourth active region extending lengthwise along the first direction,
wherein lengths of the first active region, the second active region, the third active region, and the fourth active region along the first direction are the same,
wherein the first isolation device (IS-1) and the third isolation device (IS-3) share a first gate,
wherein the second isolation device (IS-2) and the fourth isolation device (IS-4) share a second gate.
17. The memory structure of claim 16 , further comprising:
a first metal line and a second metal line extending along the first direction; and
a first word line and a second word line extending over the first metal line and the second metal line along a second direction perpendicular to the first direction,
wherein a gate of the first pass-gate device (PG-1) and a gate of the second pass-gate device (PG-2) are electrically coupled to the first metal line,
wherein a gate of the third pass-gate device (PG-3) and a gate of the fourth pass-gate device (PG-4) are electrically coupled to the second metal line,
wherein the first word line is electrically coupled to the first metal line and insulated from the second metal line,
wherein the second word line is electrically coupled to the second metal line and insulated from the first metal line.
18. The memory structure of claim 16 ,
wherein the first gate and the second gate are electrically coupled to a positive supply voltage (CVdd).
19. The memory structure of claim 18 , further comprising:
a metal line electrically coupled to the positive supply voltage (CVdd),
wherein the first gate is electrically coupled to the metal line by way of a first via,
wherein the second gate is electrically coupled to the metal line by way of a second via,
wherein the first metal line is disposed directly over a boundary between the first cell structure and the second cell structure.
20. The memory structure of claim 16 ,
wherein each of the first cell structure and the second cell structure comprises a length along the first direction and a width along a second direction perpendicular to the first direction,
wherein a ratio of the width to the length is between about 0.5 and about 1.