Integrated circuit devices and fabricating method thereof

1. A device, comprising:

a first fin-shaped transistor on a substrate; and

a second fin-shaped transistor on the substrate, wherein:

a first source/drain of the first fin-shaped transistor has a first thickness, a second source/drain of the second fin-shaped transistor has a second thickness different from the first thickness, and

lower surfaces of the first source/drain and the second source/drain are higher than an upper surface of the substrate, wherein

an impurity concentration of the first source/drain is different from an impurity concentration of the second source/drain such that the impurity concentration difference between the first source/drain and the second source/drain causes a driving current difference between the first fin-shaped transistor and the second fin-shaped transistor.

2. The device as claimed in claim 1 , wherein:

a first distance ranges from a first bottom of a first fin of the first fin-shaped transistor to a first interface between the first fin and the first source/drain,

a second distance ranges from a second bottom of a second fin of the second fin-shaped transistor to a second interface between the second fin and second source/drain, and

the first distance and the second distance are different.

3. The device as claimed in claim 1 , wherein:

the first source/drain and the second source/drain have substantially a same first lattice constant, and

a first stress applied by the first source/drain to a first channel of the first fin-shaped transistor is different from a second stress applied by the second source/drain to a second channel of the second fin-shaped transistor.

4. The device as claimed in claim 3 , wherein the first channel and the second channel have substantially a same second lattice constant different from the first lattice constant.

5. The device as claimed in claim 3 , wherein

the first fin-shaped transistor and the second fin-shaped transistor are PMOS transistors,

the first source/drain and the second source/drain include SiGe, and

the first channel and the second channel include Si.

6. The device as claimed in claim 3 , wherein:

the first fin-shaped transistor and the second fin-shaped transistor are NMOS transistors, and

the first source/drain and the second source/drain include SiC, the first channel and the second channel include Si.

7. The device as claimed in claim 1 , wherein

the first source/drain of the first fin-shaped transistor is directly on the substrate, and

the second source/drain of the second fin-shaped transistor is directly on the substrate.

8. A device, comprising:

a first transistor on a substrate, the first transistor having a first fin including a first channel between first source/drain regions; and

a second transistor on the substrate, the second transistor having a second fin including a second channel between second source/drain regions; wherein:

the first and second channels have fixed channel widths, lower surfaces of the first and second source/drain regions are higher than an upper surface of the substrate, and

the first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current, wherein

an impurity concentration of the first source/drain regions are different from an impurity concentration of the second source/drain regions such that the impurity concentration difference between the first source/drain regions and the second source/drain regions causes a difference between the first and second amounts of currents.

9. The device as claimed in claim 8 , wherein:

the first source/drain regions apply a first force to the first channel in the first fin, and

the second source/drain regions apply a second force to the second channel in the second fin, wherein the first force is different from the second force, a difference between the first and second forces corresponding to the difference between the first and second amounts of currents.

10. The device as claimed in claim 9 , wherein:

the first source/drain regions apply the first force to the first channel based on the impurity concentration of the first source/drain regions, and

the second source/drain regions apply the second force to the second channel based on the impurity concentration of the second source/drain regions.

11. The device as claimed in claim 9 , wherein:

the first source/drain regions apply the first force to the first channel based on a first size of the first source/drain regions, and

the second source/drain regions apply the second force to the second channel based on a second size of the second source/drain regions different from the first size.

12. The device as claimed in claim 11 , wherein the first and second sizes are different thicknesses.

13. The device as claimed in claim 8 , wherein:

the first transistor has a first number of first fins, and

the second transistor has a second number of second fins different from the first number of fins, wherein

the first number is at least one, and wherein:

the first number of fins corresponds to the first amount of current, and

the second number of fins corresponds to the second amount of current.

14. The device as claimed in claim 8 , wherein

the first transistor has a first number of nanowires which includes the first channel, and

the second transistor has a second number of nanowires which includes a second channel, wherein

the first number of nanowires is at least one, and wherein:

the first amount of current is based on the first number of nanowires, and

the second amount of current is based on the second number of nanowires.