Ultra-scaled transistor devices to enable cell size scaling
Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.
1 . An integrated circuit (IC) die, comprising:
a substrate comprising a semiconductor material;
a fin consisting of the semiconductor material, and over the substrate, the semiconductor material of the fin having a first width at a first height over the substrate, a second width at a second height over the substrate and above the first height, and a third width at a third height over the substrate and above the second height, wherein the first and third widths are greater than the second width; and
a gate structure, a source, and a drain coupled to a channel portion of the fin, wherein the IC die comprises, or is thermally coupled to, a cooling structure, the cooling structure to remove heat from the IC die to achieve an operating temperature below −25° C.
2 . The IC die of claim 1 , wherein the fin has a fourth width at a fourth height over the substrate but below the first height, and the first width is greater than the fourth width.
3 . The IC die of claim 1 , wherein the semiconductor material comprises silicon.
4 . The IC die of claim 1 , wherein the cooling structure is to remove heat from the IC die to achieve an operating temperature below −70° C.
5 . The IC die of claim 1 , wherein the semiconductor material comprises silicon.
6 . The IC die of claim 1 , wherein the semiconductor material has a convex sidewall defining the first and third widths.
7 . An integrated circuit (IC) die, comprising:
a substrate comprising a semiconductor material;
a fin consisting of the semiconductor material, and over the substrate, the semiconductor material of the fin having a first width at a first height over the substrate, a second width at a second height over the substrate and above the first height, and a third width at a third height over the substrate and above the second height, wherein the first and third widths are greater than the second width;
a gate structure, a source, and a drain coupled to a channel portion of the fin; and
an insulating material over the substrate and adjacent to the first width, but not adjacent to the second or third widths, and wherein the channel portion comprises the second and third widths of the semiconductor material.
8 . The IC die of claim 7 , wherein the gate structure is over the insulating material, and is coupled to the second and third widths of the semiconductor material.
9 . The IC die of claim 1 , wherein the semiconductor material has a fourth width at a fourth height over the third height, and a fifth width at a fifth height above the fourth height, and wherein the second and fourth widths are greater than the first, third, and fifth widths.
10 . The IC die of claim 9 , wherein the gate structure is coupled to the second, third, fourth and fifth widths of the semiconductor material.