IP Library › Granted Patent US 11,824,555
Granted Patent B2
US 11,824,555 · App. 17/713,524 · Granted Nov 21, 2023

System and method for a super-resolution digital-to-analog converter based on redundant sensing

Inventors: Zhi Yang (Minneapolis, MN); Anh Tuan Nguyen (Minneapolis, MN); Diu Khue Luu (Minneapolis, MN); Jian Xu (Minneapolis, MN)
Assignee: REGENTS OF THE UNIVERSITY OF MINNESOTA
H03M1/46H03M1/007H03M1/447H03M1/802
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,824,555
App. No.
17/713,524
Granted
Nov 21, 2023
Kind
B2
Abstract

A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

Claims (26)

1. A digital-to-analog converter device comprising:

a set of components, each component included in the set of components comprising a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell;

a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components; and

an output electrode coupled to the plurality of switches, the digital-to-analog converter device being configured to output an output signal at the output electrode,

wherein a first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components, and

wherein the unit cell size of each unit cell is adjusted based on a mismatch error that achieves a targeted effective resolution value.

2. The digital-to-analog converter device of claim 1 , wherein the unit cell size comprises a length value and a width value.

3. The digital-to-analog converter device of claim 1 , wherein the unit cell size is associated with a transistor process size.

4. The digital-to-analog converter device of claim 1 , wherein at least one component included in the set of components includes a number of unit cells that is not a power of two.

5. The digital-to-analog converter device of claim 1 , wherein the digital-to-analog converter device is a current digital-to-analog converter.

6. The digital-to-analog converter device of claim 1 , wherein the digital-to-analog converter device further comprises a controller coupled to the plurality of switches, the controller configured to

receive a desired output current;

determine a component configuration based on the desired output current and a predetermined output current value measured at the output electrode, the predetermined output current value associated with the component configuration; and

cause a current pulse to be output from the digital-to-analog converter device based on the component configuration.

7. A method for determining manufacturing parameters for a digital-to-analog converter device comprising a set of components, each component included in the set of components including at least one unit cell, and each unit cell being associated with a unit cell size, the method comprising:

determining a required mismatch error value for the unit cells included in the component set based on a targeted effective resolution value;

determining an initial unit cell size based on the required mismatch error value;

setting the unit cell size of each unit cell included in the component set to be equal to the initial unit cell size;

determining an effective resolution of the digital-to-analog converter device by performing simulations;

determining that the effective resolution is below the targeted effective resolution;

adjusting the unit cell size of one or more unit cells included in the component set in response to determining that the effective resolution is below the targeted effective resolution; and

providing each unit cell size associated with each unit cell to a manufacturing facility.

8. The method of claim 7 , wherein the targeted effective resolution is at least four times higher than an intrinsic resolution of the digital-to-analog converter device.

9. The method of claim 7 , wherein the unit cell size comprises a length value and a width value, and wherein each unit cell comprises at least one transistor.

10. The method of claim 7 , wherein at least one component included in the set of components includes a number of unit cells that is not a power of two.

11. The method of claim 7 , wherein the simulations are Monte Carlo simulations.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2023
From: YANG, ZHI; NGUYEN, ANH TUAN; LUU, DIU KHUE; XU, JIAN
To: REGENTS OF THE UNIVERSITY OF MINNESOTA
Reel/Frame 063682/0741 →
Continuity (3)
Division 17066456 · Oct 8, 2020
Provisional Application 62913759 · Oct 11, 2019
Related Publication 20220239309A1 · Jul 28, 2022