Semiconductor element memory device
View Patent ↗A memory device includes a page made of a plurality of memory cells arranged in rows on a substrate. A page write operation is performed, during which, in each of the memory cells included in the page, a first voltage V 1 is applied to a first drive control line PL, a second voltage V 2 is applied to a word line WL, a third voltage V 3 is applied to a source line SL, a fourth voltage V 4 is applied to a bit line BL, a group of holes generated by an impact ionization phenomenon is retained in an inside of the channel semiconductor layer. A page erase operation is performed, during which the voltages to be applied to the first drive control line PL, the word line WL, the source line SL, and the bit line BL are controlled to discharge the group of holes from the inside of the channel semiconductor layer, and the voltage of the channel semiconductor layer is decreased. A page read operation is performed, during which a fifth voltage V 5 that is lower than the first voltage V 1 is applied to the first drive control line PL, a sixth voltage V 6 that is lower than the second voltage V 2 is applied to the word line WL, the third voltage V 3 is applied to the source line, and a seventh voltage V 7 that is lower than the fourth voltage V 4 is applied to the bit line.
1. A semiconductor element memory device comprising a plurality of pages in columns, each of the pages being made of a plurality of memory cells arranged in rows, wherein
each of the memory cells included in the page includes
a semiconductor base on a substrate, the semiconductor base standing vertically or extending horizontally to the substrate,
a first impurity layer and a second impurity layer at both ends of the semiconductor base,
a first gate insulating layer that surrounds part or all of a side surface of the semiconductor base between the first impurity layer and the second impurity layer and that is in contact with or close to the first impurity layer,
a second gate insulating layer that surrounds part or all of the side surface of the semiconductor base, that is connected to the first gate insulating layer, and that is in contact with or close to the second impurity layer,
a first gate conductor layer that covers part or all of the first gate insulating layer,
a second gate conductor layer that covers the second gate insulating layer, and
a channel semiconductor layer in which the semiconductor base is covered with the first gate insulating layer and the second gate insulating layer,
in each of the memory cells,
during a page write operation, a first voltage is applied to the first gate conductor layer, a second voltage is applied to the second gate conductor layer, a third voltage is applied to the first impurity layer, a fourth voltage is applied to the second impurity layer, a group of holes generated by an impact ionization phenomenon is retained in an inside of the channel semiconductor layer, and a voltage of the channel semiconductor layer is set to a first data retention voltage that is higher than either or both of voltages of the first impurity layer and the second impurity layer,
during a page erase operation, the voltages to be applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to discharge the group of holes from the inside of the channel semiconductor layer in each of all the memory cells constituting the page, through either or both of the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is set to a second data retention voltage that is lower than the first data retention voltage, and
during a page read operation, in each of all the memory cells constituting the page, a fifth voltage is applied to the first gate conductor layer, a sixth voltage is applied to the second gate conductor layer, the third voltage is applied to the first impurity layer, and a seventh voltage is applied to the second impurity layer, and
the fifth voltage is lower than the first voltage.
2. The semiconductor element memory device according to claim 1 , wherein the sixth voltage is lower than the second voltage.
3. The semiconductor element memory device according to claim 1 , wherein the seventh voltage is lower than the fourth voltage.
4. The semiconductor element memory device according to claim 1 , wherein the third voltage is a ground voltage.
5. The semiconductor element memory device according to claim 1 , wherein a first gate capacitance between the first gate conductor layer and the channel semiconductor layer is formed to be larger than a second gate capacitance between the second gate conductor layer and the channel semiconductor layer.
6. A semiconductor element memory device comprising a block in which the plurality of pages of the memory device according to claim 1 are arranged, wherein
in each of the memory cells included in the plurality of pages, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first drive control line,
the source line is connected across the semiconductor bases in the block, and
with voltages applied to the source line, the bit line, the first drive control line, and the word line, the page erase operation for discharging the group of holes in all the semiconductor bases of the page that is selected in the block is performed.
7. The semiconductor element memory device according to claim 6 , wherein the voltage applied to the first drive control line during the page read operation is lower than the voltage applied to the first drive control line during the page write operation, the voltage applied to the word line during the page read operation is lower than the voltage applied to the word line during the page write operation, and the voltage applied to the bit line during the page read operation is lower than the voltage applied to the bit line during the page write operation.
8. The semiconductor element memory device according to claim 6 , wherein the voltage applied to the source line is the ground voltage during the page write operation and the page read operation.
9. The semiconductor element memory device according to claim 1 , wherein the first gate conductor layer is isolated into two conductor layers that surround the first gate insulating layer in plan view.
10. The semiconductor element memory device according to claim 7 , wherein the voltage applied to the source line is the ground voltage during the page write operation and the page read operation.
11. A semiconductor element memory device comprising a block in which the plurality of pages of the memory device according to claim 2 are arranged, wherein
in each of the memory cells included in the plurality of pages, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first drive control line,
the source line is connected across the semiconductor bases in the block, and
with voltages applied to the source line, the bit line, the first drive control line, and the word line, the page erase operation for discharging the group of holes in all the semiconductor bases of the page that is selected in the block is performed.
12. A semiconductor element memory device comprising a block in which the plurality of pages of the memory device according to claim 3 are arranged, wherein
in each of the memory cells included in the plurality of pages, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first drive control line,
the source line is connected across the semiconductor bases in the block, and
with voltages applied to the source line, the bit line, the first drive control line, and the word line, the page erase operation for discharging the group of holes in all the semiconductor bases of the page that is selected in the block is performed.
13. A semiconductor element memory device comprising a block in which the plurality of pages of the memory device according to claim 4 are arranged, wherein
in each of the memory cells included in the plurality of pages, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first drive control line,
the source line is connected across the semiconductor bases in the block, and
with voltages applied to the source line, the bit line, the first drive control line, and the word line, the page erase operation for discharging the group of holes in all the semiconductor bases of the page that is selected in the block is performed.
14. A semiconductor element memory device comprising a block in which the plurality of pages of the memory device according to claim 5 are arranged, wherein
in each of the memory cells included in the plurality of pages, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first drive control line,
the source line is connected across the semiconductor bases in the block, and
with voltages applied to the source line, the bit line, the first drive control line, and the word line, the page erase operation for discharging the group of holes in all the semiconductor bases of the page that is selected in the block is performed.