Semiconductor memory device
View Patent ↗A dynamic flash memory includes a p layer as a semiconductor base material; first and second n + layers extending on opposite sides thereof; a first gate insulating layer partially covering the p layer; a first gate conductor layer provided thereon; a second gate insulating layer provided in contact with the first gate insulating layer and partially covering the p layer; and a second gate conductor layer provided on the second gate insulating layer and electrically isolated from the first gate conductor layer. The first and second n + layers, and the first and second gate conductor layers are respectively connected to a source line, a bit line, a word line, and a plate line. A voltage applied to each terminal during memory erasing is always greater than or equal to 0 V such that 2 V and 0.6 V are respectively applied to the plate line and the bit line.
1. A memory device with semiconductor elements, comprising:
a semiconductor base material extending on a substrate in a horizontal direction or a vertical direction;
a first impurity region and a second impurity region that are continuous with respective opposite ends of the semiconductor base material;
a first gate insulating layer partially covering the semiconductor base material;
a first gate conductor layer covering the first gate insulating layer;
a second gate insulating layer continuous with the first gate insulating layer and partially covering the semiconductor base material; and
a second gate conductor layer not in contact with the first gate conductor layer, the second gate conductor layer covering the second gate insulating layer,
wherein a memory erase operation is performed by applying to one of the first gate conductor layer and the second gate conductor layer a first voltage in a range of 0 V to a threshold voltage, and also applying to the other of the first gate conductor layer and the second gate conductor layer a second voltage having a polarity identical to a polarity of the first voltage and having an absolute value greater than or equal to an absolute value of the threshold voltage, thereby reducing holes or electrons that are majority carriers remaining in the semiconductor base material.
2. The memory device with the semiconductor elements according to claim 1 ,
wherein the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer and the second gate conductor layer is connected to a plate line, and
an operation of a dynamic flash memory is performed by applying a voltage to each of the source line, the bit line, the plate line, and the word line to execute a memory write operation, a memory read operation, and the memory erase operation.
3. The memory device with the semiconductor elements according to claim 2 ,
wherein in the erase operation for the dynamic flash memory, when the majority carriers in the semiconductor base material are holes, a voltage of 0 V or a positive potential is applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer.
4. The memory device with the semiconductor elements according to claim 2 ,
wherein in the erase operation for the dynamic flash memory, when the majority carriers in the semiconductor base material are electrons, a voltage of 0 V or a negative potential is applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer.
5. The memory device with the semiconductor elements according to claim 2 ,
wherein in the memory erase operation for the dynamic flash memory, one of the source line and the bit line is at 0 V.
6. The memory device with the semiconductor elements according to claim 2 ,
wherein the memory write operation for the dynamic flash memory includes
applying to the word line a voltage having an absolute value that is greater than or equal to an absolute value of a threshold voltage of a first MOS transistor region including the first gate insulating layer and the first gate conductor layer, and having a polarity identical to a polarity of the threshold voltage,
applying to the plate line a voltage having an absolute value that is greater than or equal to an absolute value of a threshold voltage of a second MOS transistor region including the second gate insulating layer and the second gate conductor layer, and having a polarity identical to a polarity of the threshold voltage,
applying to the bit line a voltage that allows a maximum electric field in the semiconductor base material to cause impact ionization during writing,
applying 0 V to the source line, thereby causing an impact ionization phenomenon based on a current flowed between the first impurity region and the second impurity region, and thus generating electrons and holes in the semiconductor base material and the first impurity region, and
allowing, among the generated electrons and holes, some or all of the electrons or the holes that are the majority carriers in the semiconductor base material to remain in the semiconductor base material.
7. The memory device with the semiconductor elements according to claim 2 ,
wherein an absolute value of a current flowing through the bit line during the memory erase operation for the dynamic flash memory is lower than an absolute value of a current flowing through the bit line during the memory write operation for the dynamic flash memory.
8. The memory device with the semiconductor elements according to claim 2 ,
wherein the voltages applied to the plate line, the word line, the source line, and the bit line during the memory write operation and the memory erase operation for the dynamic flash memory are 0 V or voltages having the same polarity.