Semiconductor package and method of fabricating the same
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a package substrate, a redistribution layer on the package substrate, a vertical connection terminals that connects the package substrate to the redistribution layer, a first semiconductor chip between the package substrate and the redistribution layer, a first molding layer that fills a space between the package substrate and the redistribution layer, a second semiconductor chip on the redistribution layer, a third semiconductor chip on the second semiconductor chip, a first connection wire that directly and vertically connects the redistribution layer to a first chip pad of the third semiconductor chip, the first chip pad is beside the second semiconductor chip and on a bottom surface of the third semiconductor chip, and a second molding layer on the redistribution layer and covering the second semiconductor chip and the third semiconductor chip.
1. A semiconductor package, comprising:
a package substrate;
a redistribution layer on the package substrate;
a vertical connection terminal that connects the package substrate to the redistribution layer;
a first semiconductor chip between the package substrate and the redistribution layer;
a first molding layer that fills a space between the package substrate and the redistribution layer, wherein the redistribution layer covers the first molding layer and the first semiconductor chip, and the first semiconductor chip is on a first side of the redistribution layer;
a second semiconductor chip on the redistribution layer;
a third semiconductor chip on the second semiconductor chip;
a first connection wire that directly and vertically connects the redistribution layer to a first chip pad of the third semiconductor chip, the first chip pad is beside the second semiconductor chip and on a bottom surface of the third semiconductor chip; and
a second molding layer on the redistribution layer, wherein the second molding layer covers the second semiconductor chip and the third semiconductor chip, and the second semiconductor chip and the third semiconductor chip are on a second side of the redistribution layer opposite the first side of the redistribution layer, and
wherein the first molding layer is in contact with a bottom surface of the redistribution layer.
2. The semiconductor package of claim 1 , wherein an entirety of the first connection wire is between the redistribution layer and the bottom surface of the third semiconductor chip.
3. The semiconductor package of claim 1 , further comprising a second connection wire that directly and vertically connects the redistribution layer to a second chip pad, the second chip pad is on a bottom surface of the second semiconductor chip.
4. The semiconductor package of claim 3 , wherein the second connection wire is between the redistribution layer and the bottom surface of the second semiconductor chip.
5. The semiconductor package of claim 1 , wherein an angle between the first connection wire and the bottom surface of the third semiconductor chip or between the first connection wire and a top surface of the redistribution layer is in a range of about 30° to about 90°.
6. The semiconductor package of claim 1 , wherein
a bottom surface of the second semiconductor chip is in contact with a top surface of the redistribution layer, and
a second chip pad of the second semiconductor chip is directly connected to a substrate pad of the redistribution layer.
7. The semiconductor package of claim 1 , wherein the vertical connection terminal includes a third connection wire that directly connects the redistribution layer to the package substrate.
8. The semiconductor package of claim 1 , wherein the vertical connection terminal includes a through electrode that vertically penetrates the first molding layer.
9. The semiconductor package of claim 1 , further comprising a connection substrate between the package substrate and the redistribution layer, the connection substrate having an opening that penetrates the connection substrate,
wherein the first semiconductor chip is in the opening,
wherein the first molding layer fills a space between the connection substrate and the first semiconductor chip in the opening, and
wherein the vertical connection terminal includes a substrate wiring pattern in the connection substrate.
10. A semiconductor package, comprising:
a package substrate;
a first semiconductor chip on the package substrate;
a redistribution layer on the first semiconductor chip;
a plurality of first connection wires on one side of the first semiconductor chip, the first connection wires vertically connecting the package substrate to the redistribution layer; and
a chip stack including a plurality of second semiconductor chips that are stacked on the redistribution layer,
wherein the chip stack is on a side of the redistribution layer opposite to a side of the redistribution layer including the first semiconductor chip,
wherein each second semiconductor chip of the plurality of second semiconductor chips has a chip pad on a bottom surface of the second semiconductor chip, and
wherein the plurality of second semiconductor chips are electrically connected to the redistribution layer through a plurality of second connection wires that vertically connect chip pads of the plurality of second semiconductor chips to substrate pads of the redistribution layer.
11. The semiconductor package of claim 10 , wherein
the chip stack is spaced apart from a top surface of the redistribution layer, and
the second semiconductor chip at a lowermost of the chip stack is electrically connected to the redistribution layer through one of the second connection wires.
12. The semiconductor package of claim 10 , wherein
the chip stack is in direct contact with a top surface of the redistribution layer,
the chip pad of the second semiconductor chip at a lowermost of the chip stack is directly connected to one of the substrate pads of the redistribution layer, and
the second semiconductor chips other than the second semiconductor chip at the lowermost of the chip stack are electrically connected through the second connection wires to the redistribution layer.
13. The semiconductor package of claim 10 , wherein an angle between a second connection wire of the plurality of second connection wires and the chip pad or between the second connection wire of the plurality of second connection wires and a substrate pad of the redistribution layer is in a range of about 30° to about 90°.
14. The semiconductor package of claim 10 , wherein
the second semiconductor chips are stacked in a stepwise shape along one direction parallel to a top surface of the redistribution layer, and
each of the second semiconductor chips exposes the chip pad of an overlying second semiconductor chip.
15. The semiconductor package of claim 10 , wherein
widths of the plurality of second semiconductor chips increase with increasing distance from the redistribution layer, and
each of the second semiconductor chips exposes the chip pad of an overlying second semiconductor chip.
16. The semiconductor package of claim 10 , further comprising a molding layer on the redistribution layer, the molding layer covering the chip stack,
wherein a top surface of the molding layer is coplanar with a top surface of the chip stack.
17. A method of fabricating a semiconductor package, the method comprising:
stacking a plurality of first semiconductor chips on a dummy substrate to form a chip stack;
forming a plurality of first bonding wires that connect a dummy pad of the dummy substrate to first chip pads of the first semiconductor chips, an uppermost end of each of the first bonding wires is at a level higher than a level of a top surface of the chip stack;
forming on the dummy substrate a first molding layer that encapsulates the chip stack and the first bonding wires;
allowing the first molding layer to undergo a thinning process that divides the first bonding wires into a plurality of second bonding wires each of which extends from one of the first chip pads and is exposed on a top surface of the first molding layer;
forming on the first molding layer a redistribution layer electrically connected to the second bonding wires;
placing a second semiconductor chip on the redistribution layer, wherein the chip stack is on a side of the redistribution layer opposite to a side of the redistribution layer including the second semiconductor chip;
forming a plurality of vertical connection terminals on one side of the second semiconductor chip and on the redistribution layer; and
forming a package substrate on the redistribution layer and the second semiconductor chip, the package substrate being connected to the vertical connection terminals.
18. The method of claim 17 , wherein forming the redistribution layer includes:
forming a dielectric pattern on the first molding layer;
forming a plurality of holes in the dielectric pattern, each of the holes exposing one of the second bonding wires; and
forming on the dielectric pattern a conductive pattern connected through the holes to the second bonding wires.
19. The method of claim 17 , wherein forming the vertical connection terminals includes:
forming a plurality of third bonding wires that connect to each other a plurality of substrate pads of the redistribution layer, an uppermost end of each of the third bonding wires is at a level higher than a level of a top surface of the second semiconductor chip;
forming on the dummy substrate a second molding layer that encapsulates the second semiconductor chip and the third bonding wires; and
allowing the second molding layer to undergo a thinning process that divides the third bonding wires into the plurality of vertical connection terminals each of which extends from one of the substrate pads and is exposed on a top surface of the second molding layer.
20. The method of claim 17 , further comprising:
removing the dummy substrate; and
performing a sawing process to remove portions of the first bonding wires connected to the dummy pad.