Method and system for fabrication of a vertical fin-based field effect transistor

1. A method of fabricating a vertical fin-based field effect transistor (FET), the method comprising:

providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type;

epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer;

epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer;

forming a metal compound layer on the second semiconductor layer;

forming a patterned hard mask layer on the metal compound layer;

etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench; and

terminating the etching in the graded doping layer.

2. The method of claim 1 , further comprising:

epitaxially growing a third semiconductor layer having a second conductivity type opposite the first conductivity type in the trench;

etching back the third semiconductor layer to expose a sidewall portion of the plurality of fins;

forming a silicon dioxide layer on the etched-back third semiconductor layer and overlying the patterned hard mask layer and sidewall portion of the plurality of fins, the silicon dioxide layer having an elevated portion in a vicinity of the plurality of fins;

forming a silicon nitride layer on the silicon dioxide layer;

isotropically etching the silicon nitride layer and the silicon dioxide layer to expose an upper surface of the silicon dioxide layer and to form a silicon nitride spacer on sidewalls of the elevated portion of the silicon dioxide layer;

removing a portion of the silicon dioxide layer that is not covered by the silicon nitride spacer while exposing a first surface portion of the third semiconductor layer; and

removing the silicon nitride spacer and the patterned hard mask layer.

3. The method of claim 2 , further comprising:

forming a patterned source mask overlying an exposed surface of the second semiconductor layer and exposing a surface of the metal compound layer;

forming a source stack structure comprising Ti, Al, and Mo from bottom to top on the metal compound layer; and

removing the patterned source mask.

4. The method of claim 3 , further comprising:

forming a gate mask on the source stack structure and the elevated portion of the silicon dioxide layer while exposing a second surface portion of the third semiconductor layer;

forming a gate structure on the exposed second surface portion of the third semiconductor layer; and

removing the gate mask.

5. The method of claim 4 , wherein the gate structure comprises a metal stack comprising Ni, Au, Mo, Au arranged from bottom to top.

6. The method of claim 4 , further comprising:

forming a nitride interlayer dielectric layer overlying the source stack structure, the gate structure, and an exposed surface of the second semiconductor layer;

forming an oxide interlayer dielectric layer overlying the nitride interlayer dielectric layer;

forming a patterned photoresist layer on the oxide interlayer dielectric layer;

etching the oxide interlayer dielectric layer and the nitride interlayer dielectric layer using the patterned photoresist layer to form a via hole extending to the source stack structure; and

filling the via hole with a conductive material.

7. The method of claim 6 , wherein the via hole has a diameter of about 0.45 μm.

8. The method of claim 1 , wherein the second semiconductor layer comprises In x Ga 1-x N, where 0<x<1.

9. The method of claim 1 , further comprising forming a drain electrode on the second surface of the semiconductor substrate.

10. The method of claim 1 , wherein the semiconductor substrate comprises N+ GaN having a first dopant concentration, the second semiconductor layer comprising N GaN having a second dopant concentration lower than the first dopant concentration, the drift layer of the first semiconductor layer comprises N−GaN having a third dopant concentration lower than the second dopant concentration, and the graded doping layer of the first semiconductor layer comprises a fourth dopant concentration linearly increasing from the third dopant concentration to the second dopant concentration.

11. The method of claim 1 , wherein the drift layer has a thickness of about 12 μm, the graded doping layer has a thickness of about 0.3 μm, and the plurality of fins each have a thickness of about 0.7 μm and a width of about 0.2 μm and are spaced apart from each other by a space of about 2 μm.

12. The method of claim 1 , further comprising:

removing the patterned hard mask layer; and

forming source contacts on the surface of the metal compound layer of the plurality of fins.