Non-planar I/O and logic semiconductor devices having different workfunction on common substrate
Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
1. An integrated circuit structure, comprising:
a first N-type fin-FET device having a first fin, the first fin having a sidewall at an end of the fin, and the first N-type fin-FET device comprising a first gate electrode over the end of the first fin and adjacent to the sidewall of the first fin, and a second gate electrode over the first fin and spaced apart from the first gate electrode, wherein the second gate electrode has a first gate length; and
a second N-type fin-FET device having a second fin, the second N-type fin-FET device comprising a third gate electrode over the second fin, wherein the third gate electrode has a second gate length different than the first gate length, and wherein the third gate electrode has a workfunction layer having a thickness different than a thickness of a workfunction layer of the second gate electrode.
2. The integrated circuit structure of claim 1 , wherein the second gate length is less than the first gate length.
3. The integrated circuit structure of claim 1 , wherein the thickness of the workfunction layer of the third gate electrode is less than the thickness of the workfunction layer of the second gate electrode.
4. The integrated circuit structure of claim 1 , wherein the first N-type fin-FET device is a logic transistor, and the second N-type fin-FET device is an I/O transistor.
5. The integrated circuit structure of claim 1 , further comprising:
a first gate dielectric between the first fin and the first gate electrode;
a second gate dielectric between the first fin and the second gate electrode; and
a third gate dielectric between the second fin and the third gate electrode.
6. The integrated circuit structure of claim 1 , further comprising a fourth gate electrode over an end of the second fin and adjacent to a sidewall of the second fin.
7. An integrated circuit structure, comprising:
a first P-type fin-FET device having a first fin, the first fin having a sidewall at an end of the fin, and the first P-type fin-FET device comprising a first gate electrode over the end of the first fin and adjacent to the sidewall of the first fin, and a second gate electrode over the first fin and spaced apart from the first gate electrode, wherein the second gate electrode has a first gate length; and
a second P-type fin-FET device having a second fin, the second P-type fin-FET device comprising a third gate electrode over the second fin, wherein the third gate electrode has a second gate length different than the first gate length, and wherein the third gate electrode has a workfunction layer having a thickness different than a thickness of a workfunction layer of the second gate electrode.
8. The integrated circuit structure of claim 7 , wherein the second gate length is less than the first gate length.
9. The integrated circuit structure of claim 7 , wherein the thickness of the workfunction layer of the third gate electrode is less than the thickness of the workfunction layer of the second gate electrode.
10. The integrated circuit structure of claim 7 , wherein the first P-type fin-FET device is a logic transistor, and the second P-type fin-FET device is an I/O transistor.
11. The integrated circuit structure of claim 7 , further comprising:
a first gate dielectric between the first fin and the first gate electrode;
a second gate dielectric between the first fin and the second gate electrode; and
a third gate dielectric between the second fin and the third gate electrode.
12. The integrated circuit structure of claim 7 , further comprising a fourth gate electrode over an end of the second fin and adjacent to a sidewall of the second fin.
13. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first N-type fin-FET device having a first fin, the first fin having a sidewall at an end of the fin, and the first N-type fin-FET device comprising a first gate electrode over the end of the first fin and adjacent to the sidewall of the first fin, and a second gate electrode over the first fin and spaced apart from the first gate electrode, wherein the second gate electrode has a first gate length; and
a second N-type fin-FET device having a second fin, the second N-type fin-FET device comprising a third gate electrode over the second fin, wherein the third gate electrode has a second gate length different than the first gate length, and wherein the third gate electrode has a workfunction layer having a thickness different than a thickness of a workfunction layer of the second gate electrode.
14. The computing device of claim 13 , further comprising:
a memory coupled to the board.
15. The computing device of claim 13 , further comprising:
a communication chip coupled to the board.
16. The computing device of claim 13 , further comprising:
a camera coupled to the board.
17. The computing device of claim 13 , further comprising:
a battery coupled to the board.
18. The computing device of claim 13 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
19. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first P-type fin-FET device having a first fin, the first fin having a sidewall at an end of the fin, and the first P-type fin-FET device comprising a first gate electrode over the end of the first fin and adjacent to the sidewall of the first fin, and a second gate electrode over the first fin and spaced apart from the first gate electrode, wherein the second gate electrode has a first gate length; and
a second P-type fin-FET device having a second fin, the second P-type fin-FET device comprising a third gate electrode over the second fin, wherein the third gate electrode has a second gate length different than the first gate length, and wherein the third gate electrode has a workfunction layer having a thickness different than a thickness of a workfunction layer of the second gate electrode.
20. The computing device of claim 19 , further comprising:
a memory coupled to the board.
21. The computing device of claim 19 , further comprising:
a communication chip coupled to the board.
22. The computing device of claim 19 , further comprising:
a camera coupled to the board.
23. The computing device of claim 19 , further comprising:
a battery coupled to the board.
24. The computing device of claim 19 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.