Semiconductor device and data storage system including the same
A semiconductor device and a data storage system including the same are provided. The semiconductor device including a plate layer, a pattern structure on the plate layer, an upper pattern layer on the pattern structure, an upper structure including a stack structure and a capping insulating structure covering at least a portion of the stack structure, the stack structure including interlayer insulating layers and gate layers alternately stacked on each other, and separation structures and vertical memory structures penetrating through the upper structure, the upper pattern layer, and the pattern structure, and extending into the plate layer may be provided.
1. A semiconductor device comprising:
a plate layer;
a pattern structure on the plate layer;
an upper pattern layer on the pattern structure;
an upper structure including a stack structure and a capping insulating structure, the stack structure being on the upper pattern layer and including interlayer insulating layers and gate layers alternately stacked on each other, the capping insulating structure covering at least a portion of the stack structure;
separation structures penetrating through the upper structure, the upper pattern layer, and the pattern structure, and extending into the plate layer; and
vertical memory structures penetrating through the upper structure, the upper pattern layer, and the pattern structure between the separation structures, extending into the plate layer, and contacting the plate layer,
wherein each of the separation structures includes a lower portion and an upper portion on the lower portion,
the lower portion includes a first lower portion, a second lower portion, and a third lower portion,
the first lower portion is in the plate layer and contacts the plate layer,
the second lower portion penetrates through the pattern structure,
the third lower portion penetrates through the upper pattern layer,
the upper portion penetrates through the upper structure, and
a maximum width of the first lower portion is different from a maximum width of the third lower portion.
2. The semiconductor device of claim 1 , wherein
the stack structure includes a lower stack structure and an upper stack structure on the lower stack structure,
the lower stack structure includes lower interlayer insulating layers and lower gate layers alternately stacked on each other,
the upper stack structure includes upper interlayer insulating layers and upper gate layers stacked alternately on each other, and
a side surface of each of the vertical memory structures includes a slope change portion in which a side slope changes, at a height level between a lowermost upper gate layer among the upper gate layers and an uppermost lower gate layer among the lower gate layers.
3. The semiconductor device of claim 2 , wherein a side surface of each of the separation structures includes a slope change portion, in which a side slope changes, at a height level between the lowermost upper gate layer among the upper gate layers and the uppermost lower gate layer among the lower gate layers.
4. The semiconductor device of claim 1 , wherein in plan view, in each of the separation structures, a side shape of the first lower portion is different from a side shape of the upper portion.
5. The semiconductor device of claim 1 , wherein in plan view, in each of the separation structures, a side surface of the first lower portion has a straight linear shape, and a side surface of the upper portion has a wavy shape.
6. The semiconductor device of claim 1 , wherein in plan view, in each of the separation structures, a side surface of the first lower portion has a straight linear shape, and a side surface of the third lower portion has a wavy shape.
7. The semiconductor device of claim 1 , wherein
the separation structures include first separation structures parallel to each other, and a second separation structure and a third separation structure between the first separation structures,
an upper portion of the second separation structure and an upper portion of the third separation structure are spaced apart from each other,
the separation structures further include a connection portion connecting a lower portion of the second separation structure and a lower portion of the third separation structure, and
the stack structure includes a portion between the upper portion of the second separation structure and the upper portion of the third separation structure.
8. The semiconductor device of claim 1 , wherein
the separation structures include first separation structures parallel to each other, and a second separation structure and a third separation structure between the first separation structures and being in a row, and
a portion of the plate layer is between the second separation structure and the third separation structure.
9. The semiconductor device of claim 1 , further comprising:
a peripheral circuit structure below the plate layer, wherein
at least a portion of the plate layer is between the peripheral circuit structure and the upper structure, and
the peripheral circuit structure includes a semiconductor substrate and a peripheral circuit on the semiconductor substrate.
10. The semiconductor device of claim 1 , further comprising:
a peripheral circuit structure on the upper structure, wherein
the peripheral circuit structure includes a semiconductor substrate and a peripheral circuit on the semiconductor substrate, and
the peripheral circuit is between the semiconductor substrate and the upper structure.
11. The semiconductor device of claim 1 , wherein at least one of the separation structures includes a line portion extending in a first direction, and pillar portions connected to the line portion at a different height level from the line portion, the pillar portions being spaced apart from each other in the first direction.
12. The semiconductor device of claim 1 , wherein
the stack structure includes a lower stack structure and an upper stack structure on the lower stack structure,
the lower stack structure includes lower interlayer insulating layers and lower gate layers alternately stacked on each other,
the upper stack structure includes upper interlayer insulating layers and upper gate layers alternately stacked on each other, and
a first separation structure among the separation structures includes a lower line portion passing through the lower gate layers, an upper line portion passing through the upper gate layers, and an intermediate pillar portion spaced apart from each other between the lower line portion and the upper line portion.
13. The semiconductor device of claim 12 , wherein the first separation structure of the separation structures further include upper pillar portions spaced apart from each other on the upper line portion.
14. A semiconductor device comprising:
a plate layer;
an upper structure including a stack structure and a capping insulating structure covering at least a portion of the stack structure, the stack structure on the plate layer and including interlayer insulating layers and gate layers alternately stacked on each other;
separation structures penetrating through at least a portion of the upper structure; and
vertical memory structures penetrating through the upper structure between the separation structures, wherein
a first separation structure among the separation structures includes a first line portion extending in a first direction and being parallel to an upper surface of the plate layer, and a plurality of first pillar portions being at a different height level from the first line portion and spaced apart from each other in the first direction, and
the plurality of first pillar portions are at a level lower than that of an uppermost gate layer among the gate layers, and at a level higher than that of a lowermost gate layer among the gate layers.
15. The semiconductor device of claim 14 , further comprising:
a support structure overlapping the first line portion and being between the plurality of first pillar portions,
wherein at least a portion of the support structure is at a same level as at least a portion of an interlayer insulating layer among the interlayer insulating layers.
16. The semiconductor device of claim 14 , wherein
the stack structure includes a lower stack structure and an upper stack structure on the lower stack structure,
the lower stack structure includes lower interlayer insulating layers and lower gate layers alternately stacked on each other,
the upper stack structure includes upper interlayer insulating layers and upper gate layers alternately stacked on each other,
the first line portion penetrates through the lower gate layers, and
the plurality of first pillar portions extend from the first line portion in a vertical direction perpendicular to an upper surface of the plate layer.
17. The semiconductor device of claim 16 , wherein the first separation structure further includes a second line portion penetrating through the upper gate layers and extending in the first direction, and upper pillar portions being on the second line portion and spaced apart from each other in the first direction.
18. A data storage system comprising:
a semiconductor device including an input/output pad; and
a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device, the semiconductor device including,
a plate layer,
a pattern structure on the plate layer,
an upper pattern layer on the pattern structure,
an upper structure including a stack structure and a capping insulating structure covering at least a portion of the stack structure, the stack structure on the plate layer and including interlayer insulating layers and gate layers alternately stacked on each other,
separation structures penetrating through the upper structure, the upper pattern layer, and the pattern structure, and extending into the plate layer, and
vertical memory structures penetrating through the upper structure, the upper pattern layer, and the pattern structure between the separation structures, extending into the plate layer, and contacting the plate layer,
wherein each of the separation structures includes a lower portion and an upper portion on the lower portion,
the lower portion includes a first lower portion, a second lower portion, and a third lower portion,
the first lower portion is in the plate layer and contacts the plate layer,
the second lower portion penetrates through the pattern structure,
the third lower portion penetrates through the upper pattern layer,
the upper portion penetrates through the upper structure, and
a maximum width of the first lower portion is different from a maximum width of the third lower portion.
19. The data storage system of claim 18 , wherein, in plan view, in each of the separation structures, a side surface of the first lower portion has a straight linear shape, and a side surface of the upper portion has a wavy shape.
20. The data storage system of claim 18 , wherein at least one of the separation structures includes a line portion extending in a first direction, and pillar portions connected to the line portion at a different height level from the line portion, the pillar portions being spaced apart from each other in the first direction.