Random instruction-side stressing in post-silicon validation
A computer-implemented method including: providing a test template for a hardware system-under-test comprising one or more execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by at least some of the one or more execution threads; generating and storing, at the predetermined shared memory address, a sequence of instructions which conform to the test template; building, based, at least in part, on the test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises at least generation and execution of a test; and executing the executable image of the hardware exerciser by at least a first execution thread of the one or more execution threads of the hardware system-under-test.
1. A system comprising:
at least one hardware processor; and
a non-transitory computer-readable storage medium having stored thereon program instructions, the program instructions executable by the at least one hardware processor to:
provide a test template for a multi-threaded hardware system-under-test comprising two execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by the two execution threads,
generate and store, at said predetermined shared memory address, shared code comprising a sequence of instructions which conform to said test template,
build, based, at least in part, on said test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises generating and executing a test of common use of the shared code by the two execution threads, and
executing said executable image of the hardware exerciser, including the common use of the shared code by the two execution threads.
2. The system of claim 1 , wherein the program instructions are further executable to store, in said non-transitory computer readable medium or in a different non-transitory computer readable medium, before said executing, a state of said hardware system-under-test.
3. The system of claim 2 , wherein the program instructions are further executable to restore said hardware system-under-test to said state after said executing.
4. The system of claim 1 , wherein said building comprises embedding in said executable image data corresponding to architectural knowledge of said hardware system-under-test and testing knowledge of said hardware system-under-test.
5. The system of claim 1 , wherein said test includes directives to control one or more parameters of a randomly generated test of said hardware system-under-test selected from the group consisting of: a desired test structure, one or more resources of the hardware system-under-test to be included in said test, one or more values to be assigned to said resources, occurrence of one or more architectural or micro-architectural events during said test, and activation of testing knowledge relating to the system-under-test.
6. The system of claim 5 , wherein said architectural knowledge is obtained from an architectural model including a formal description of the specification for said hardware system-under-test, and wherein said testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of said hardware system-under-test.
7. The system of claim 1 , wherein the executable image comprises a code operative to provide light operating system (OS) services for the executable image.
8. A computer-implemented method comprising:
providing a test template for a multi-threaded hardware system-under-test comprising two execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by the two execution threads;
generating and storing, at said predetermined shared memory address, shared code comprising a sequence of instructions which conform to said test template;
building, based, at least in part, on said test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises generating and executing a test of common use of the shared code by the two execution threads; and
executing said executable image of the hardware exerciser, including the common use of the shared code by the two execution threads.
9. The computer-implemented method of claim 8 , further comprising storing, in a non-transitory computer readable medium, before said executing, a state of said hardware system-under-test.
10. The computer-implemented method of claim 9 , further comprising restoring said hardware system-under-test to said state after said executing.
11. The computer-implemented method of claim 8 , wherein said building comprises embedding in said executable image data corresponding to architectural knowledge of said hardware system-under-test and testing knowledge of said hardware system-under-test.
12. The computer-implemented method of claim 8 , wherein said test includes directives to control one or more parameters of a randomly generated test of said hardware system-under-test selected from the group consisting of: a desired test structure, one or more resources of the hardware system-under-test to be included in said test, one or more values to be assigned to said resources, occurrence of one or more architectural or micro-architectural events during said test, and activation of testing knowledge relating to the system-under-test.
13. The computer-implemented method of claim 12 , wherein said architectural knowledge is obtained from an architectural model including a formal description of the specification for said hardware system-under-test, and wherein said testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of said hardware system-under-test.
14. The computer-implemented method of claim 8 , wherein the executable image comprises a code operative to provide light operating system (OS) services for the executable image.
15. The computer-implemented method of claim 8 , executed by a processor of a computing device.
16. A computer program product comprising a non-transitory computer-readable storage medium having program instructions embodied therewith, the program instructions executable by at least one hardware processor to:
provide a test template for a multi-threaded hardware system-under-test comprising two execution threads, wherein the test template comprises a branching instruction to a predetermined shared memory address accessible by the two execution threads;
generate and store, at said predetermined shared memory address, shared code comprising a sequence of instructions which conform to said test template;
build, based, at least in part, on said test template, an executable image of a hardware exerciser, wherein the hardware exerciser is adapted to control a test cycle of the hardware system-under-test, and wherein the test cycle comprises generating and executing a test of common use of the shared code by the two execution threads; and
executing said executable image of the hardware exerciser, including the common use of the shared code by the two execution threads .
17. The computer program product of claim 16 , wherein the program instructions are further executable to store, in said non-transitory computer readable medium or in a different non-transitory computer readable medium, before said executing, a state of said hardware system-under-test.
18. The computer program product of claim 17 , wherein the program instructions are further executable to restore said hardware system-under-test to said state after said executing.
19. The computer program product of claim 16 , wherein said building comprises embedding in said executable image data corresponding to architectural knowledge of said hardware system-under-test and testing knowledge of said hardware system-under-test.
20. The computer program product of claim 16 , wherein said test includes directives to control one or more parameters of a randomly generated test of said hardware system-under-test selected from the group consisting of: a desired test structure, one or more resources of the hardware system-under-test to be included in said test, one or more values to be assigned to said resources, occurrence of one or more architectural or micro-architectural events during said test, and activation of testing knowledge relating to the system-under-test.