Current sensing in non-CMOS semiconductor technology for power conversion applications
Embodiments herein relate to a current sensor for a power converter such as a buck converter. The power converter is fabricated on a high bandgap semiconductor die while the current sensor includes a portion on the same die and a portion on a silicon die. The portion on the same die includes a sense transistor, while the portion on the silicon die includes a feedback circuit for controlling a voltage of the sense transistor to ensure it is biased according to the bias of a switching transistor of the power converter. A current of the sense transistor can then be processed such as by an averaging or sampling process.
1 . An apparatus, comprising:
a power converter on a compound semiconductor die, the power converter comprises a switching transistor; and
a current sensor comprising a first portion on the compound semiconductor die and a second portion on a silicon die, wherein the first portion comprises a sense transistor, and the second portion comprises an amplifier to control a current of the sense transistor based on a comparison of a voltage of the sense transistor to a voltage of the switching transistor, wherein the compound semiconductor die has a bandgap greater than a bandgap of the silicon die,
wherein: the sense transistor is coupled to an inverting input of the amplifier; and the switching transistor is coupled to a non-inverting input of the amplifier.
2 . The apparatus of claim 1 , wherein:
the second portion comprises a control transistor coupled to the sense transistor;
the control transistor has a gate coupled to an output of the amplifier; and
to control the current of the sense transistor, the amplifier is to control a voltage at the gate of the control transistor.
3 . The apparatus of claim 2 , wherein:
the current sensor comprises one or more current mirrors;
the control transistor is coupled to an input path of the one or more current mirrors;
an output path of the one or more current mirrors is coupled to a current processing circuit; and
the current processing circuit comprises at least one of an averaging circuit or a sampling circuit.
4 . The apparatus of claim 2 , further comprising:
a direct current level shifter coupled to the sense transistor and the control transistor.
5 . The apparatus of claim 2 , wherein:
the switching transistor comprises a low-side switching transistor of the power converter; and
a polarity of the control transistor is equal to a polarity of the switching transistor.
6 . The apparatus of claim 2 , wherein:
the switching transistor comprises a high-side switching transistor of the power converter; and
a polarity of the control transistor is opposite to a polarity of the switching transistor.
7 . The apparatus of claim 1 , wherein:
a current of the sense transistor is scaled down relative to a current of the switching transistor by a scaling factor.
8 . The apparatus of claim 1 , wherein:
the current sensor is to apply a gate voltage to the sense transistor which is equal to a gate voltage of the switching transistor and to apply a drain voltage to the sense transistor which is equal to a drain voltage of the switching transistor.
9 . The apparatus of claim 1 , wherein:
the compound semiconductor die comprises at least one of Gallium Nitride, Silicon Carbide or Gallium Arsenide.
10 . The apparatus of claim 1 , wherein:
the silicon die comprises a gate driver for the switching transistor.
11 . The apparatus of claim 1 , wherein:
the sense transistor is coupled to the inverting input of the amplifier via a first capacitor; and
the switching transistor is coupled to the non-inverting input of the amplifier via a second capacitor.
12 . An apparatus, comprising:
a first die comprising a power converter and a first sense transistor, wherein the first die has a bandgap greater than a bandgap of silicon; and
a silicon die comprising:
a first amplifier and a first control transistor, wherein the silicon die has a first interface to couple a non-inverting input of the first amplifier to a first node of the power converter;
a second interface to couple an inverting input of the first amplifier to the first sense transistor;
a third interface to couple the first control transistor to the first sense transistor, wherein the first amplifier, to modulate a voltage of the first sense transistor, is to modulate a control gate voltage of the first control transistor based on a voltage of the first node; and
a current processing circuit to process a current of the first sense transistor.
13 . The apparatus of claim 12 , wherein:
a common control gate voltage is applied to the first sense transistor and a first switching transistor of the power converter; and
a common drain voltage is applied to the first sense transistor and the first switching transistor of the power converter.
14 . The apparatus of claim 12 , wherein:
the power converter comprises a high-side switching transistor and a low-side switching transistor; and
the current processing circuit is to process the current of the first sense transistor when the high-side switching transistor is turned on and the low-side switching transistor is turned off but not when the high-side switching transistor is turned off and the low-side switching transistor is turned on.
15 . The apparatus of claim 12 , wherein:
the power converter comprises a high-side switching transistor and a low-side switching transistor; and
the current processing circuit is to process the current of the first sense transistor when the high-side switching transistor is turned off and the low-side switching transistor is turned on but not when the high-side switching transistor is turned on and the low-side switching transistor is turned off.
16 . The apparatus of claim 12 , wherein:
the first die further comprises a second sense transistor; and
the silicon die further comprises:
a second amplifier and a second control transistor, wherein the silicon die has a fourth interface to couple a non-inverting input of the second amplifier to a second node of the power converter;
a fifth interface to couple an inverting input of the second amplifier to the second sense transistor; and
a sixth interface to couple the second control transistor to the second sense transistor, wherein the second amplifier, to modulate a voltage of the second sense transistor, is to modulate a control gate voltage of the first control transistor based on a voltage of the second node, and the current processing circuit is to process a total current based on a sum of the current of the first sense transistor and a current of the second sense transistor.
17 . The apparatus of claim 16 , wherein:
the power converter comprises a high-side switching transistor and a low-side switching transistor; and
the current processing circuit is to process the current of the first sense transistor when the high-side switching transistor is turned on and the low-side switching transistor is turned off and to process the current of the second sense transistor when the high-side switching transistor is turned off and the low-side switching transistor is turned on.
18 . A sense circuit, comprising:
a sense transistor;
a control transistor coupled to the sense circuit;
an amplifier having an output coupled to the control transistor, a non-inverting input to couple to a switching node of a power converter and an inverting input to couple to the sense transistor; and
a current processing circuit coupled to the control transistor, the current processing circuit is to provide an output which is representative of a current of the switching node, wherein:
the amplifier, control transistor and current processing circuit are on a silicon die; and
the power converter is on a die having a bandgap greater than a bandgap of the silicon die.
19 . The sense circuit of claim 18 , wherein:
the amplifier is in a feedback control loop of a voltage of the sense transistor.