Nonvolatile memory device

1. A cell array in a nonvolatile memory device, the cell array comprising:

a first floating gate of an odd row and a second floating gate of an even row spaced apart from each other and formed on a substrate;

a first control gate surrounding the first floating gate of the odd row and tilted positively with respect to an X-axis; and

a second control gate surrounding the second floating gate of the even row and tilted negatively with respect to the X-axis.

2. The cell array of claim 1 , wherein the first floating gate is tilted positively with respect to the X-axis, and

wherein the second floating gate is tilted negatively with respect to the X-axis.

3. The cell array of claim 1 , further comprising a first source line contact disposed between the first control gate and the second control gate,

wherein the first source line contact is disposed to be aligned with ends of the first floating gate and the second floating gate.

4. The cell array of claim 3 , further comprising a first bit line contact disposed diagonally to the first source line contact,

wherein the first bit line contact is disposed to be aligned with the other ends of the first floating gate and the second floating gate.

5. The cell array of claim 3 , wherein a distance between the ends of the first floating gate and the second floating gate is the longest in a space between the first floating gate and the second floating gate.

6. The cell array of claim 4 , wherein the first bit line contact and the first source line contact are disposed in active areas that partially protrude at both sides of active regions.

7. The cell array of claim 1 , further comprising a first dummy cell line, wherein the first dummy cell line comprises:

a first dummy floating gate disposed adjacent to the first floating gate of the odd row, and tilted positively with respect to the X-axis; and

a second dummy floating gate disposed adjacent to the second floating gate of the even row, and tilted negatively with respect to the X-axis.

8. The cell array of claim 7 , wherein the first dummy cell line has no bit line contacts or source line contacts.

9. A cell array in a nonvolatile memory device, the cell array comprising:

first floating gates disposed in a first row on a substrate;

second floating gates disposed in a second row;

a first control gate surrounding the first floating gates, the first control gate comprising first sub-control gates connected to each other, and each of the first sub-control gates being tilted positively with respect to an X-axis; and

a second control gate surrounding the second floating gates, the second control gate comprising second sub-control gates connected to each other, and each of the second sub-control gates being tilted negatively with respect to the X-axis.

10. The cell array of claim 9 , further comprising:

first source line contacts disposed between the first control gate and the second control gate; and

first bit line contacts disposed diagonally to the first source line contacts.

11. The cell array of claim 10 , wherein each of the first source line contacts is disposed to be aligned with ends of each of the first floating gates and each of the second floating gates.

12. The cell array of claim 9 , wherein each of the first sub-control gates has a first long axis and a first short axis, and a direction of the first long axis is tilted up or down with respect to the X-axis.

13. A cell array in a nonvolatile memory device, the cell array comprising:

a first floating gate of an odd row tilted positively with respect to an X-axis on a substrate;

a second floating gate of an even row tilted negatively with respect to the X-axis, and spaced apart from the first floating gate of the odd row;

a first control gate surrounding the first floating gate of the odd row; and

a second control gate surrounding the second floating gate of the even row.

14. The cell array of claim 13 , wherein the first control gate is tilted positively with respect to the X-axis, and wherein the second control gate is tilted negatively with respect to the X-axis.

15. The cell array of claim 13 , further comprising:

a first control gate polysilicon layer connected to the first control gate;

a first floating gate polysilicon layer adjacent to the first control gate polysilicon layer; and

at least one contact plug disposed on the first control gate polysilicon layer.