Semiconductor devices having a wiring provided with a protective layer
A semiconductor device includes: a lower structure including a device and a lower wiring structure; an insulating layer on the lower structure; a via penetrating the insulating layer; a wiring pattern on the insulating layer and the via; and a silicon oxide layer covering the wiring pattern, and including hydrogen, wherein the wiring pattern includes first and second conductive layers, an upper surface protective layer, and a side surface protective layer, wherein the second conductive layer is on the first conductive layer, wherein the upper surface protective layer covers an upper surface of the second conductive layer, and the side surface protective layer covers side surfaces of the first and second conductive layers, and wherein each of the upper surface protective layer and the side surface protective layer includes a metal material having an activation energy higher than that of a metal material of the second conductive layer.
1 . A semiconductor device, comprising:
a lower structure including a device and a lower wiring structure;
an insulating layer disposed on the lower structure;
a via penetrating through the insulating layer;
a wiring pattern formed on the insulating layer and the via; and
a silicon oxide layer covering the wiring pattern, and including hydrogen,
wherein the wiring pattern includes a first conductive layer, a second conductive layer, an upper surface protective layer, and a side surface protective layer, wherein the second conductive layer is disposed on the first conductive layer, wherein the upper surface protective layer covers an upper surface of the second conductive layer, and the side surface protective layer covers a side surface of the first conductive layer and a side surface of the second conductive layer,
wherein each of the upper surface protective layer and the side surface protective layer includes a metal material having an activation energy higher than that of a metal material of the second conductive layer, and
wherein the wiring pattern further comprises an upper interfacial alloy layer disposed between the upper surface of the second conductive layer and the upper surface protective layer; and
a side interfacial alloy layer disposed between the side surface of the second conductive layer and the side surface protective layer;
a side interfacial alloy layer disposed between the side surface of the second conductive layer and the side surface protective layer.
2 . The semiconductor device of claim 1 , wherein the upper interfacial alloy layer and the side interfacial alloy layer comprise different materials from each other.
3 . The semiconductor device of claim 1 , wherein each of the upper interfacial alloy layer and the side interfacial alloy layer comprises a metal material having an activation energy higher than that of the metal material of the second conductive layer.
4 . A semiconductor device, comprising:
a first structure including a device and a first wiring structure;
an insulating layer disposed on the first structure;
a via penetrating through the insulating layer;
a wiring pattern formed on the insulating layer and the via; and
a silicon oxide layer disposed on the wiring pattern, and including hydrogen,
wherein the wiring pattern includes a conductive layer and a protective layer covering at least one of an upper surface or a side surface of the conductive layer,
wherein the wiring pattern further includes an interfacial alloy layer disposed between a surface of the conductive layer and the protective layer, and
wherein a strength of the interfacial alloy layer is greater than a strength of the conductive layer and a strength of the protective layer.
5 . The semiconductor device of claim 4 , wherein the strength of the interfacial alloy layer is greater than the strength of the protective layer, and
wherein the strength of the protective layer is greater than the strength of the conductive layer.
6 . The semiconductor device of claim 4 , wherein the conductive layer comprises Al,
wherein the protective layer comprises Ti, and
wherein the interfacial alloy layer comprises TiAl3.
7 . The semiconductor device of claim 6 , wherein the strength of the conductive layer ranges from about 19 kg/mm 2 to about 22 kg/mm 2 ,
wherein the strength of the protective layer ranges from about 81 kg/mm 2 to about 143 kg/mm 2 , and
wherein the strength of the interfacial alloy layer ranges from about 660 kg/mm 2 to about 750 kg/mm 2 .
8 . The semiconductor device of claim 4 , wherein the protective layer completely covers the upper surface of the conductive layer.
9 . The semiconductor device of claim 8 , wherein the interfacial alloy layer completely covers the upper surface of the conductive layer.