Semiconductor device having outer terminal portions with conductive layer on outer end surfaces and a method of manufacturing a semiconductor device
A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.
1. A semiconductor package comprising:
a lead frame comprising a first external connection terminal, wherein the first external connection terminal comprises:
a bottom end;
an outer terminal portion comprising a side end; and
an inner terminal portion opposite to and coupled to the outer terminal portion;
a semiconductor device coupled to the first external connection terminal with a first interconnect;
a sealing member covering the first external connection terminal and the semiconductor device and comprising a top side, a bottom side opposite to the bottom side, and a lateral side;
a plating layer; and
a groove extending inward from the bottom side of the sealing member adjoining the inner terminal portion;
wherein:
the bottom end of the first external connection terminal is exposed from the bottom side of the sealing member;
the side end of the outer terminal portion is exposed from the sealing member;
at least part of the inner terminal portion is exposed from the sealing member within the groove;
the plating layer fully covers the side end of the outer terminal portion; and
the first interconnect is the only internal attachment to the first external connection terminal.
2. The semiconductor package of claim 1 , wherein:
the semiconductor device comprises a semiconductor chip.
3. The semiconductor package of claim 1 , wherein:
the side end is a generally flat surface.
4. The semiconductor package of claim 1 , wherein:
the side end of the outer terminal portion is coplanar with the lateral side of the sealing member along a first plane; and
the first plane is perpendicular to the bottom side of the sealing member.
5. The semiconductor package of claim 4 , wherein:
the plating layer extends outward beyond the lateral side of the sealing member.
6. The semiconductor package of claim 1 , wherein:
the plating layer consists of a layer that is only external to the sealing member.
7. The semiconductor package of claim 1 , further comprising:
a die pad;
wherein the semiconductor device is attached to a top surface of the die pad, and the plating layer is further disposed on a bottom surface of the die pad.
8. The semiconductor package of claim 1 , wherein:
the inner terminal portion comprises a side end opposite to the side end of the outer terminal portion; and
the side end of the inner terminal portion has a different shape than the side end of the outer terminal portion in a cross-sectional view.
9. The semiconductor package of claim 8 , wherein:
the side end of the inner terminal portion is absent the plating layer.
10. The semiconductor package of claim 8 , wherein:
a first portion of the side end of the inner terminal portion is covered by the sealing member; and
a second portion of the side end of the inner terminal portion is exposed from the sealing member.
11. A semiconductor package comprising:
a lead frame comprising external connection terminals;
a semiconductor device coupled to the external connection terminals with interconnects;
a sealing member covering portions of the external connection terminals and the semiconductor device; and
a plating structure;
wherein:
the external connection terminals comprise:
bottom ends exposed from the sealing member;
outer terminal portions having side ends exposed from the sealing member; and
inner terminal portions opposite to and coupled to the outer terminal portions;
the plating structure fully covers at least a top portion of the side ends;
the external connection terminals are on at least two adjoining sides of the semiconductor device;
the plating structure consists of a structure that is external to the sealing member so that the portions of the external connection terminals covered by the sealing member are devoid of the plating structure;
the inner terminal portions comprise side ends;
portions of the side ends of the inner terminal portions are exposed from the sealing member; and
the portions of the side ends of the inner terminal portions that are exposed are devoid of the plating structure.
12. The semiconductor package of claim 11 , wherein:
the plating structure fully covers the side ends; and
the plating structure covers the bottom ends.
13. The semiconductor package of claim 11 , wherein:
the side ends are generally planar surfaces.
14. The semiconductor package of claim 11 , wherein:
the sealing member comprises a top side, a bottom side opposite to the top side, and a lateral side connecting the top side to the bottom side;
at least a portion of the lateral side is perpendicular to the bottom side of the sealing member; and
the side ends of the outer terminal portions are coplanar with the portion of the lateral side that is perpendicular to the bottom side of the sealing member.
15. The semiconductor package of claim 11 , wherein:
the outer terminal portions comprise top sides that are devoid of the sealing member; and
the plating structure is on the top sides external to the sealing member.
16. The semiconductor package of claim 11 , further comprising:
a groove;
wherein:
the sealing member comprises a top side, a bottom side opposite to the top side, and a lateral side connecting the top side to the bottom side;
the groove extends inward from the bottom side of the sealing member; and
the groove defines the portions of the side ends of the inner terminal portions that are exposed from the sealing member.
17. A semiconductor package comprising:
a lead frame comprising external connection terminals, the external connection terminals comprise:
bottom ends;
outer terminal portions comprising side ends; and
inner terminal portions coupled to the outer terminal portions;
a semiconductor component coupled to the external connection terminals;
a sealing member covering the external connection terminals and the semiconductor component and comprising a top side, a bottom side opposite to the top side, and a lateral side connecting the top side to the bottom side;
a groove extending inward from the bottom side of the sealing member adjoining the inner terminal portions; and
a plated conductor;
wherein:
the side ends of the outer terminal portions are exposed from the sealing member;
the inner terminal portions are exposed from the sealing member within the groove;
the plated conductor fully covers the side ends of the outer terminal portions; and
the external connection terminals are on two adjoining sides of the semiconductor component.
18. The semiconductor package of claim 17 , wherein:
the bottom ends are exposed from the bottom side of the sealing member; and
the plated conductor covers the bottom ends.
19. The semiconductor package of claim 17 , wherein:
at least a portion of the lateral side of the sealing member is perpendicular to the bottom side of the sealing member;
the side ends of the outer terminal portions are flush with the portion of the lateral side of the sealing member that is perpendicular to the bottom side of the sealing member; and
the plated conductor extends outward from the lateral side of the sealing member.
20. The semiconductor package of claim 17 , wherein:
the plated conductor consists of a conductor that is only external to the sealing member.