IP Library Granted Patent US 12,622,294
Granted Patent B2
US 12,622,294 · App. 17/733,170 · Granted May 5, 2026

Methods and apparatus to improve signal integrity performance in integrated circuit packages

Inventors: Cemil Geyik (Gilbert, AZ); Kemal Aygun (Tempe, AZ); Yidnekachew Mekonnen (Chandler, AZ); Zhichao Zhang (Chandler, AZ); Suddhasattwa Nad (Chandler, AZ)
Assignee: Intel Corporation
H01L23/5386H01L24/14H01L24/16H01L25/0655H01L2224/1403H01L2224/16227
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Quick Facts
Patent No.
US 12,622,294
App. No.
17/733,170
Granted
May 5, 2026
Kind
B2
Abstract

Methods, apparatus, systems, and articles of manufacture to improve signal integrity performance in integrated circuit packages are disclosed. An integrated circuit (IC) package includes a substrate; a first conductive pad in a first metal layer in the substrate; and a second conductive pad in a second metal layer in the substrate. The first metal layer is adjacent the second metal layer with no intervening metal layers therebetween. The integrated circuit (IC) package further includes a conductive protrusion extending from the first conductive pad toward the second conductive pad.

Claims (35)

1 . An integrated circuit (IC) package comprising:

a substrate including an array of contacts on a first surface of the substrate, the contacts associated with metal in a base metal layer of the substrate;

a first conductive pad in a first metal layer in the substrate;

a second conductive pad in a second metal layer in the substrate, the first metal layer adjacent the second metal layer with no intervening metal layers therebetween, the base metal layer different than the first metal layer and different than the second metal layer; and

a conductive protrusion extending from the first conductive pad toward the second conductive pad.

2 . The IC package of claim 1 , wherein the conductive protrusion is electrically connected to a first contact in the array of contacts.

3 . The IC package of claim 2 , wherein the first metal layer corresponds to the base metal layer, the first conductive pad corresponds to the first contact, and the second metal layer corresponds to a base-1 metal layer of the substrate.

4 . The IC package of claim 2 , wherein the second metal layer corresponds to the base metal layer, the second conductive pad corresponds to the first contact, and the first metal layer corresponds to a base-1 metal layer of the substrate.

5 . The IC package of claim 2 , wherein the array of contacts corresponds to a land grid array.

6 . The IC package of claim 2 , wherein the array of contacts corresponds to a ball grid array.

7 . The IC package of claim 1 , wherein one of the first conductive pad or the second conductive pad corresponds to a ground plane in the substrate.

8 . The IC package of claim 1 , wherein the first conductive pad is associated with a conductive arm electrically connected to a first contact on the substrate, the conductive arm extending along the first metal layer away from the first contact and toward a second contact, the second conductive pad associated with the second contact.

9 . The IC package of claim 8 , wherein the conductive arm is a stub having a distal end that is spaced apart from a path for an electrical signal transmitted through the first contact.

10 . The IC package of claim 8 , wherein the conductive arm defines a portion of a path for an electrical signal transmitted through the first contact.

11 . The IC package of claim 1 , wherein the substrate is a package substrate of the IC package, the package substrate exposed to an exterior of the IC package.

12 . The IC package of claim 1 , wherein the substrate is an interposer disposed within the IC package, the interposer mounted to a separate package substrate of the IC package.

13 . The IC package of claim 1 , wherein the conductive protrusion extends from the first conductive pad to the second conductive pad at least 25% of a distance between the first and second metal layers.

14 . An apparatus comprising:

a substrate including a first surface and a second surface opposite the first surface;

an array of contacts on the first surface of the substrate;

a semiconductor die mounted on the second surface of the substrate, the contacts associated with signal paths through the substrate to electrically couple the semiconductor die with the contacts;

a first conductive pad electrically connected to a first signal path of the signal paths, the first conductive pad electrically connected to a first contact of the array of contacts through a conductive arm extending away from the first contact, the conductive arm electrically connected to the first contact through a metal via in a via stack electrically connected to the first contact, the via stack defining the first signal path; and

a second conductive pad electrically connected to a second signal path of the signal paths, the second signal path different than the first signal path, a distance between the first and second conductive pads being less than a distance between adjacent metal layers in the substrate.

15 . The apparatus of claim 14 , wherein at least one of the first conductive pad or the second conductive pad corresponds to one of the contacts.

16 . The apparatus of claim 14 , wherein the conductive arm is electrically connected to the first contact independent of a via stack electrically connected to the first contact, the via stack defining the first signal path.

17 . The apparatus of claim 14 , wherein the first and second conductive pads are positioned to reduce crosstalk between the first and second signal paths.

18 . An apparatus, comprising:

a package substrate;

a plurality of metal layers within the package substrate, the metal layers including metal defining metal interconnects through the package substrate;

a plurality of dielectric layers, different ones of the dielectric layers between adjacent ones of the metal layers; and

a metal plate between first metal in a first metal layer and second metal in a second metal layer, the first and second metal layers adjacent one another, the metal plate in contact with the first metal.

19 . The apparatus of claim 18 , wherein the first metal is electrically connected to a first one of the metal interconnects and the second metal is electrically connected to a second one of the metal interconnects.

20 . The apparatus of claim 18 , wherein the metal plate is an integral extension of the first metal.

21 . The apparatus of claim 18 , wherein the metal plate is a first metal plate, and the second metal is a second metal plate, the first and second metal plates have a matching shape.

22 . The apparatus of claim 18 , wherein the metal plate has a thickness that is at least half a distance between the first and second metal layers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076064/0951 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2022
From: GEYIK, CEMIL; AYGUN, KEMAL; MEKONNEN, YIDNEKACHEW; ZHANG, ZHICHAO; NAD, SUDDHASATTWA
To: INTEL CORPORATION
Reel/Frame 059810/0753 →
Continuity (1)
Related Publication 20230352416A1 · Nov 2, 2023
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