Patent Assignment
Reel/Frame 076064/0951
Assignment of Assignor's Interest
Recorded: 2026-09-18
Pages: 4
Assignor
INTEL CORPORATION
Executed: 2026-04-10
Assignee
INTEL FOUNDRY IP LLC
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(35)
Lithographic Cavity Formation to Enable Emib Bump Pitch Scaling
Lithographic Cavity Formation to Enable Emib Bump Pitch Scaling
Lithographic Cavity Formation to Enable Emib Bump Pitch Scaling
Lithographic Cavity Formation to Enable Emib Bump Pitch Scaling
Self-Aligned Gate Endcap (Sage) Architectures with Gate-All-Around Devices
Self-Aligned Gate Endcap (Sage) Architectures with Gate-All-Around Devices
Self-Aligned Gate Endcap (Sage) Architectures with Gate-All-Around Devices
Self-Aligned Gate Endcap (Sage) Architectures with Gate-All-Around Devices
Multi-Die Packages with Efficient Memory Storage
Methods and Apparatus to Adhere a Dielectric to a Nonconductive Layer in Circuit Devices
Self-Aligned Gate Endcap (Sage) Architectures with Vertical Sidewalls
Self-Aligned Gate Endcap (Sage) Architectures with Vertical Sidewalls
Integrated Circuit Packages with on Package Memory Architectures
Inductor and Transformer Semiconductor Devices Using Hybrid Bonding Technology
Waveguide Interconnects for Semiconductor Packages and Related Methods
Apparatus and Method of Manufacturing a Vertically Disaggregated Photonic Device
Position Controlled Waveguides and Methods of Manufacturing the Same
Methods and Apparatus to Increase Glass Core Thickness
Glass Substrates Having Signal Shielding for Use with Semiconductor Packages and Related Methods
Methods and Apparatus to Reduce Defects in Interconnects Between Semicondcutor Dies and Package Substrates
Methods and Apparatus to Reduce Defects in Interconnects Between Semicondcutor Dies and Package Substrates
Methods and Apparatus to Reduce Defects in Interconnects Between Semicondcutor Dies and Package Substrates
Capacitor Pads and Methods of Manufacturing the Same
Embedded Glass Cores in Package Substrates and Related Methods
Methods and Apparatus to Reduce Stress on Lasers in Optical Transceivers
Glass Substrates Having Transverse Capacitors for Use with Semiconductor Packages and Related Methods
Methods and Apparatus to Reduce Thickness of on-Package Memory Architectures
Methods, Systems, Apparatus, and Articles of Manufacture for Integrated Circuit Package Substrates with High Aspect Ratio Through Glass Vias
Electrical Traces on Glass Cores in Integrated Circuit Packages and Methods of Manufacturing the Same
Methods and Apparatus to Improve Signal Integrity Performance in Integrated Circuit Packages
Photonically Steered Impedance Surface Antennas
Substrates Having Adhesion Promotor Layers and Related Methods
Methods and Apparatus to Implement Library Analytics and Guided Partitioning to Select Power-Performance-Area of Semiconductor Chip Design
Methods and Apparatus to Generate Circuit Timing Constraint Predictions Using Machine Learning
Systems for Integrated Pump and Reservoir
Related Assignments
(12)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 26, 2018
From: GUHA, BISWAJEET; HSU, WILLIAM; GULER, LEONARD P.; CRUM, DAX M.
To: INTEL CORPORATION
Reel/Frame 046469/0605 →
Assignment of Assignor's Interest
Oct 15, 2018
From: GUPTA HYDE, MARUTI; HIMAYAT, NAGEEN; HURD, LINDA; LIM, MIN SUET
To: INTEL CORPORATION
Reel/Frame 047167/0983 →
Assignment of Assignor's Interest
Nov 30, 2018
From: DARMAWIKARTA, KRISTOF; TANAKA, HIROKI; MAY, ROBERT; PAITAL, SAMEER
To: INTEL CORPORATION
Reel/Frame 047645/0820 →
Assignment of Assignor's Interest
Oct 29, 2020
From: DAS, RITESH K.; CHIKKADI, KIRAN; PEARCE, RYAN
To: INTEL CORPORATION
Reel/Frame 054212/0800 →
Assignment of Assignor's Interest
Jul 16, 2021
From: SWAN, JOHANNA; ELSHERBINI, ADEL; LIFF, SHAWNA; DOGIAMIS, GEORGIOS
To: INTEL CORPORATION
Reel/Frame 056877/0411 →
Assignment of Assignor's Interest
Jul 20, 2021
From: DOGIAMIS, GEORGIOS; YU, QIANG; ELSHERBINI, ADEL; JUN, KIMIN
To: INTEL CORPORATION
Reel/Frame 056917/0802 →
Assignment of Assignor's Interest
Sep 27, 2021
From: GOH, ENG HUAT; CHANG, MOOI LING; KHOO, POH BOON; LIM, CHU AUN
To: INTEL CORPORATION
Reel/Frame 057609/0070 →
Assignment of Assignor's Interest
Oct 11, 2021
From: ECTON, JEREMY; ARANA, LEONEL; BRYKS, WHITNEY; CHEN, HAOBO
To: INTEL CORPORATION
Reel/Frame 057754/0911 →
Assignment of Assignor's Interest
May 19, 2022
From: BRAUNISCH, HONNING; ELSHERBINI, ADEL
To: INTEL CORPORATION
Reel/Frame 059960/0344 →
Assignment of Assignor's Interest
Aug 2, 2022
From: DARMAWIKARTA, KRISTOF; PIETAMBARAM, SRINIVAS; DUONG, BENJAMIN; CHEN, HAOBO
To: INTEL CORPORATION
Reel/Frame 060700/0484 →
Assignment of Assignor's Interest
May 31, 2024
From: DARMAWIKARTA, KRISTOF; TANAKA, HIROKI; MAY, ROBERT; PAITAL, SAMEER
To: INTEL CORPORATION
Reel/Frame 067577/0557 →
Corrective Assignment to Correct the 1ST Inventor's First Name Previously Recorded at Reel: 59960 Frame: 344. Assignor(S) Hereby Confirms the Assignment.
Jan 3, 2025
From: BRAUNISCH, HENNING; ELSHERBINI, ADEL
To: INTEL CORPORATION
Reel/Frame 069834/0969 →