IP Library Granted Patent US 12,487,420
Granted Patent B2
US 12,487,420 · App. 17/359,447 · Granted Dec 2, 2025

Apparatus and method of manufacturing a vertically disaggregated photonic device

Inventors: Henning Braunisch (Phoenix, AZ); Adel Elsherbini (Tempe, AZ)
Assignee: Intel Corporation
G02B6/4274G02B6/4236
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Quick Facts
Patent No.
US 12,487,420
App. No.
17/359,447
Granted
Dec 2, 2025
Kind
B2
Abstract

Apparatus and methods of manufacture are disclosed. In one example the apparatus includes a first substrate that has a first surface, a first optical waveguide that is at or near the first surface of the first substrate, a second substrate that has a second surface. The second substrate is coupled to the first substrate at an interface. The apparatus also has a photonic integrated circuit (PIC) with a portion at or near the second surface. The PIC is in alignment with and optically coupled to the first optical waveguide across the interface.

Claims (54)

1 . An apparatus, comprising:

a first semiconductor die, the first semiconductor die having a first surface;

a first optical waveguide associated with the first semiconductor die, the first optical waveguide optically accessible at the first surface of the first semiconductor die;

a second semiconductor die, the second semiconductor die having a second surface, the second semiconductor die different from the first semiconductor die, the second semiconductor die coupled to the first semiconductor die at an interface; and

a photonic integrated circuit (PIC) associated with the second semiconductor die, at least a portion of the PIC optically accessible at the second surface, the PIC in alignment with and optically coupled to the first optical waveguide across the interface, the interface has a thickness of 1 micrometer or less.

2 . The apparatus of claim 1 , wherein the second semiconductor die is hybridly bonded to the first semiconductor die at the interface.

3 . The apparatus of claim 2 , wherein the first semiconductor die is optically passive.

4 . The apparatus of claim 3 , wherein the PIC includes a photodetector.

5 . The apparatus of claim 3 , wherein the PIC is a component of at least one hybrid laser.

6 . The apparatus of claim 1 , including a charge modulated region in the second semiconductor die, the charge modulated region to adjust a state of the PIC in response to a signal.

7 . The apparatus of claim 6 , wherein the second semiconductor die includes:

an electro-optical material in the charge modulated region of the second semiconductor die, the electro-optical material is responsive to the signal; and

at least one electrically conductive input electrically coupled to the electro-optical material.

8 . The apparatus of claim 6 , including a ring resonator.

9 . The apparatus of claim 8 , wherein the ring resonator is a component of a ring resonator modulator.

10 . The apparatus of claim 8 , wherein the state includes a resonance frequency of the ring resonator.

11 . The apparatus of claim 8 , wherein the ring resonator is oriented perpendicular to a plane of the second semiconductor die.

12 . The apparatus of claim 8 , wherein the ring resonator is oriented parallel to a plane of the second semiconductor die.

13 . The apparatus of claim 6 , including an electrical modulator input in the first semiconductor die, the electrical modulator input electrically coupled, across the interface, to the charge modulated region.

14 . The apparatus of claim 6 , including an electrical modulator input in a third semiconductor die, the electrical modulator input electrically coupled to the charge modulated region at a third surface of the second semiconductor die, the third surface opposite the interface.

15 . A method of assembling a vertically disaggregated photonic device, the method comprising:

fabricating a first substrate with an optical waveguide at a first surface of the first substrate, the optical waveguide is a first part of the vertically disaggregated photonic device;

fabricating a second substrate with a photonic integrated circuit (PIC) at a second surface of the second substrate, the PIC is a second part of the vertically disaggregated photonic device; and

hybridly bonding the first surface of the first substrate to the second surface of the second substrate at an interface, the interface having a sub-micron thickness, the first surface bonded to the second surface so that the optical waveguide and the PIC are aligned and optically coupled across the interface to assemble the vertically disaggregated photonic device.

16 . The method of claim 15 , wherein the fabricating of the second substrate includes:

fabricating a planar optical waveguide ring on a wafer; and

positioning the planar optical waveguide ring in the second substrate in a perpendicular position relative to a horizontal plane of the second substrate, the horizontal plane parallel to an interface of the first surface of the first substrate and the second surface of the second substrate, wherein the planar optical waveguide ring is at least a portion of the PIC.

17 . The method of claim 15 , wherein the fabricating of the second substrate includes:

fabricating a first optical waveguide layer in the second substrate;

fabricating a second optical waveguide layer in the second substrate;

coupling a first optical via to a first end of the first optical waveguide layer and to a first end of the second optical waveguide layer; and

coupling a second optical via to a second end of the first optical waveguide layer and to a second end of the second optical waveguide layer such that the first and second optical waveguide layers and the first and second optical vias form an optical waveguide ring, wherein the optical waveguide ring is at least a portion of the PIC.

18 . The method of claim 17 , including fabricating 90-degree turning components to couple the first and second optical vias to the first and second optical waveguide layers, respectively.

19 . An apparatus, comprising:

a semiconductor device package, the semiconductor device package including:

a first substrate, the first substrate having a first surface;

a first optical waveguide associated with the first substrate, the first optical waveguide at the first surface of the first substrate;

a second substrate, the second substrate having a second surface and a third surface, the second substrate coupled to the first substrate at an interface;

a photonic integrated circuit (PIC) associated with the second substrate, at least a portion of the PIC at the second surface, the PIC in alignment with and optically coupled to the first optical waveguide across the interface, a thickness of the interface small enough to position the first optical waveguide within 1 micrometer from the PIC; and

a third substrate, the third substrate coupled to the second substrate at the third surface, the third surface opposite the interface.

20 . The apparatus of claim 19 , wherein the second substrate is hybridly bonded to the first substrate at the interface.

21 . The apparatus of claim 20 , wherein the PIC includes a photodetector.

22 . The apparatus of claim 20 , wherein the PIC is a component of at least one hybrid laser.

23 . The apparatus of claim 19 , including a charge modulated region in the second substrate, the charge modulated region to adjust a state of the PIC in response to a signal.

24 . The apparatus of claim 23 , wherein the second substrate includes:

an electro-optical material in the charge modulated region of the second substrate, the electro-optical material is responsive to the signal; and

at least one electrically conductive input electrically coupled to the electro-optical material.

25 . The apparatus of claim 24 , including an electrical modulator input in the third substrate, the electrical modulator input electrically coupled to the charge modulated region at a third surface of the second substrate.

26 . The apparatus of claim 19 , including a ring resonator.

27 . The apparatus of claim 26 , wherein the ring resonator is a component of a ring resonator modulator.

28 . The apparatus of claim 19 , wherein the third substrate is a compute die.

29 . The apparatus of claim 19 , wherein the third substrate is an input/output controller.

30 . The apparatus of claim 19 , wherein the third substrate is solder bump bonded to the second substrate.

31 . The apparatus of claim 19 , wherein the third substrate is hybridly bonded to the second substrate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076064/0951 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 1ST INVENTOR'S FIRST NAME PREVIOUSLY RECORDED AT REEL: 59960 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 3, 2025
From: BRAUNISCH, HENNING; ELSHERBINI, ADEL
To: INTEL CORPORATION
Reel/Frame 069834/0969 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2022
From: BRAUNISCH, HONNING; ELSHERBINI, ADEL
To: INTEL CORPORATION
Reel/Frame 059960/0344 →
Continuity (1)
Related Publication 20220413237A1 · Dec 29, 2022
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