IP Library Granted Patent US 12,660,662
Granted Patent B2
US 12,660,662 · App. 17/855,298 · Granted Jun 16, 2026

Methods and apparatus to adhere a dielectric to a nonconductive layer in circuit devices

Inventors: Kristof Darmawikarta (Chandler, AZ); Srinivas Pietambaram (Chandler, AZ); Benjamin Duong (Phoenix, AZ); Haobo Chen (Chandler, AZ)
Assignee: Intel Corporation
H10W70/685H10W70/05H10W70/611H10W70/65H10W70/69H10W90/401H10W90/00H10W90/701H10W90/724
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Quick Facts
Patent No.
US 12,660,662
App. No.
17/855,298
Granted
Jun 16, 2026
Kind
B2
Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices. An example apparatus includes an electrically conductive layer, a dielectric layer, and an electrically nonconductive layer separating the dielectric layer from the conductive layer, the nonconductive layer having a first surface facing the conductive layer and a second surface facing the dielectric layer, the first surface having a first roughness, the second surface having a second roughness greater than the first roughness.

Claims (23)

1 . An apparatus comprising:

an electrically conductive layer;

a dielectric layer; and

an electrically nonconductive layer separating the dielectric layer from the conductive layer, the nonconductive layer having a first surface facing the conductive layer and a second surface facing the dielectric layer, the first surface having a first roughness, the second surface having a second roughness greater than the first roughness.

2 . The apparatus of claim 1 , wherein the electrically nonconductive layer includes silicon and nitrogen.

3 . The apparatus of claim 1 , wherein the second roughness corresponds to a surface roughness greater than 75 nanometers (nm).

4 . The apparatus of claim 1 , wherein the second surface defines an interface between the nonconductive layer and the dielectric layer such that the nonconductive layer is in contact with the dielectric layer.

5 . The apparatus of claim 4 , further including metal particulates at the interface between the nonconductive layer and the dielectric layer.

6 . The apparatus of claim 5 , wherein ones of the metal particulates have a width in a range from 1 nm to 10 nm.

7 . The apparatus of claim 5 , wherein the second surface of the nonconductive layer includes recesses at least partially surrounding regions of the nonconductive layer in contact with the metal particulates.

8 . The apparatus of claim 5 , wherein the metal particulates include at least one of titanium or magnesium.

9 . The apparatus of claim 1 , further including metal particulates embedded in the nonconductive layer, the second roughness based on ones of the metal particulates protruding beyond the second surface.

10 . The apparatus of claim 9 , wherein ones of the metal particulates are completely encased by the nonconductive layer.

11 . An integrated circuit (IC) package comprising:

a substrate;

a conductive trace extending along a first surface of the substrate;

a dielectric material covering the conductive trace and extending across the first surface of the substrate; and

a nonconductive material between the conductive trace and the dielectric material, the nonconductive material having a second surface facing away from the first surface of the substrate, the second surface of the nonconductive material including protrusions extending from a main body of the nonconductive material, the dielectric material to interface with sidewalls of the protrusions.

12 . The IC package of claim 11 , wherein the nonconductive material further includes a third surface opposite the second surface, the second surface having a surface area greater than the third surface due to the protrusions on the second surface.

13 . The IC package of claim 11 , further including metal bodies at ends of ones of the protrusions.

14 . The IC package of claim 13 , wherein different ones of the metal bodies have different sizes.

15 . The IC package of claim 14 , wherein different ones of the protrusions have different widths corresponding to the different sizes of the different ones of the metal bodies.

16 . The IC package of claim 13 , wherein the metal bodies are at least one of irregularly or randomly distributed across the second surface of the nonconductive material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076064/0951 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2022
From: DARMAWIKARTA, KRISTOF; PIETAMBARAM, SRINIVAS; DUONG, BENJAMIN; CHEN, HAOBO
To: INTEL CORPORATION
Reel/Frame 060700/0484 →
Continuity (1)
Related Publication 20240006284A1 · Jan 4, 2024
References Cited (1)
US 10199266B2 · Jaywant · 2019 [cited by examiner]