IP Library Granted Patent US 12,616,052
Granted Patent B2
US 12,616,052 · App. 17/484,519 · Granted Apr 28, 2026

Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates

Inventors: Kyle McElhinny (Tempe, AZ); Bohan Shan (Chandler, AZ); Hongxia Feng (Chandler, AZ); Xiaoying Guo (Chandler, AZ); Adam Schmitt (Tempe, AZ); Jacob Vehonsky (Gilbert, AZ); Steve Cho (Chandler, AZ); Leonel Arana (Phoenix, AZ)
Assignee: Intel Corporation
H01L24/14H01L21/60H01L23/49816H01L23/49838H01L23/5381H01L23/5386H01L24/16H01L2021/60022
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Quick Facts
Patent No.
US 12,616,052
App. No.
17/484,519
Granted
Apr 28, 2026
Kind
B2
Abstract

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

Claims (60)

1 . An apparatus comprising:

a substrate;

a semiconductor die mounted to the substrate;

operational bridge bumps to electrically connect the die to a bridge within the substrate;

dummy bumps adjacent the operational bridge bumps, the dummy bumps and the operational bridge bumps have a same size of diameter, the dummy bumps and the operational bridge bumps including metal bases on a first surface of a passivation layer; and

vias extending through the passivation layer from the metal bases to metal pads located along a second surface of the passivation layer, the second surface opposite the first surface, the metal pads associated with the dummy bumps electrically isolated from other metal in the substrate.

2 . The apparatus of claim 1 , wherein the operational bridge bumps are distributed within a bridge bump field, the dummy bumps are between the bridge bump field and an open space in which no bumps are located.

3 . The apparatus of claim 1 , wherein the dummy bumps are in an array that surrounds the operational bridge bumps.

4 . The apparatus of claim 1 , wherein the dummy bumps do not form a connection that extends a full distance between the die and the substrate.

5 . The apparatus of claim 1 , wherein the dummy bumps are on the die.

6 . The apparatus of claim 1 , wherein the dummy bumps are on the substrate.

7 . The apparatus of claim 1 , wherein the dummy bumps are first dummy bumps on the substrate, the apparatus including second dummy bumps on the die.

8 . The apparatus of claim 1 , wherein the substrate corresponds to a package substrate of an integrated circuit package.

9 . The apparatus of claim 1 , wherein the die is a first die, and the substrate corresponds to a second die distinct from the first die.

10 . An apparatus comprising:

a substrate;

a semiconductor die mounted to the substrate;

operational bridge bumps to electrically connect the die to a bridge within the substrate; and

dummy bumps adjacent the operational bridge bumps, the dummy bumps anchored in place with corresponding metal vias extending between a first metal pad and a second metal pad, the first metal pad adjacent a first surface of a passivation layer, the second metal pad adjacent a second surface of the passivation layer opposite the first surface, the dummy bumps not electrically coupled to other interconnects in the substrate.

11 . An apparatus comprising:

a substrate;

a semiconductor die mounted to the substrate;

operational bridge bumps to electrically connect the die to a bridge within the substrate; and

dummy bumps adjacent the operational bridge bumps, the dummy bumps in alignment with and as a continuation of a packing geometry of the operational bridge bumps.

12 . An apparatus comprising:

a substrate;

a semiconductor die mounted to the substrate;

operational bridge bumps to electrically connect the die to a bridge within the substrate; and

dummy bumps adjacent the operational bridge bumps, the dummy bumps including:

a first number of dummy bumps including at least two dummy bumps in a first line extending away from the operational bridge bumps at a first location; and

a second number of dummy bumps in a second line extending away from the operational bridge bumps at a second location different than the first location, the second number different than the first number.

13 . An integrated circuit (IC) package comprising:

a semiconductor die;

a package substrate;

first bumps to electrically couple the die to a bridge within the package substrate, the first bumps distributed within a bridge bump field; and

second bumps between the first bumps and an open space between the package substrate and the die in which there are no bumps, the second bumps do not form a connection that extends a full distance between the die and the package substrate, the second bumps adjacent a perimeter of the bridge bump field, a first set of the second bumps in a first number of rows extending along a first edge of the bridge bump field, a second set of the second bumps in a second number of rows along a second edge of the bridge bump field, the first number of rows different than the second number of rows.

14 . The IC package of claim 13 , wherein the second bumps are not electrically coupled to internal interconnects within the package substrate.

15 . An integrated circuit (IC) package comprising:

a semiconductor die;

a package substrate;

first bumps to electrically couple the die to a bridge within the package substrate; and

second bumps between the first bumps and an open space between the package substrate and the die in which there are no bumps, the second bumps do not form a connection that extends a full distance between the die and the package substrate, the second bumps in a same packing geometry as the first bumps.

16 . A method of manufacturing an integrated circuit (IC) package, the method comprising:

fabricating operational bridge bumps on at least one of a semiconductor die or a substrate to support the die;

fabricating dummy bridge bumps on the at least one of the die or the substrate, the dummy bridge bumps to line an edge of an area corresponding to locations of the operational bridge bumps, the fabricating of the operational bridge bumps and the fabricating of the dummy bridge bumps include: (i) a common metal plating process and (ii) a second plating process to add additional height to the operational bridge bumps relative to the dummy bridge bumps; and

attaching the die to the substrate via the operational bridge bumps.

17 . The method of claim 16 , wherein, after the attaching of the die to the substrate, the dummy bridge bumps are to be spaced apart from an opposite one of the die or the substrate on which the dummy bridge bumps are disposed.

18 . The method of claim 16 , including patterning openings in a dry film resist for both the operational bridge bumps and the dummy bridge bumps.

19 . The method of claim 16 , wherein the substrate corresponds to a package substrate of an integrated circuit package.

20 . The method of claim 16 , wherein the die is a first die, and the substrate corresponds to a second die distinct from the first die.

21 . A method of manufacturing an integrated circuit (IC) package, the method comprising:

forming metal vias within a passivation layer of at least one of a semiconductor die or a substrate to support the die, the metal vias in contact with first metal pads proximate a first side of the passivation layer, the metal vias not electrically coupled to other interconnects within the at least one of the die or the substrate;

fabricating operational bridge bumps on the at least one of the die or the substrate;

fabricating dummy bridge bumps on the at least one of the die or the substrate, the dummy bridge bumps to line an edge of an area corresponding to locations of the operational bridge bumps, the dummy bridge bumps including second metal pads proximate a second side of the passivation layer opposite the first side, the metal vias in contact with the second metal pads; and

attaching the die to the substrate via the operational bridge bumps.

22 . A method of manufacturing an integrated circuit (IC) package, the method comprising:

patterning openings in a dry film resist on at least one of a semiconductor die or a substrate to support the die, the openings for both operational bridge bumps and dummy bridge bumps on the at least one of the semiconductor die or the substrate, the openings in the dry film resist for both the operational bridge bumps and the dummy bridge bumps following a same packing geometry;

fabricating the operational bridge bumps;

fabricating the dummy bridge bumps, the dummy bridge bumps to line an edge of an area corresponding to locations of the operational bridge bumps, the fabricating of the operational bridge bumps and the fabricating of the dummy bridge bumps include a common metal plating process; and

attaching the die to the substrate via the operational bridge bumps.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076064/0951 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2022
From: MCELHINNY, KYLE; SHAN, BOHAN; FENG, HONGXIA; GUO, XIAOYING; SCHMITT, ADAM; VEHONSKY, JACOB; CHO, STEVE; ARANA, LEONEL
To: INTEL CORPORATION
Reel/Frame 061713/0923 →
Continuity (1)
Related Publication 20230096835A1 · Mar 30, 2023
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