IP Library Granted Patent US 12,476,175
Granted Patent B2
US 12,476,175 · App. 17/485,039 · Granted Nov 18, 2025

Glass substrates having transverse capacitors for use with semiconductor packages and related methods

Inventors: Benjamin T. Duong (Phoenix, AZ); Srinivas V. Pietambaram (Chandler, AZ); Aleksandar Aleksov (Chandler, AZ); Helme Castro De La Torre (Gilbert, AZ); Kristof Darmawikarta (Chandler, AZ); Darko Grujicic (Chandler, AZ); Sashi S. Kandanur (Chandler, AZ); Suddhasattwa Nad (Chandler, AZ); Rengarajan Shanmugam (Chandler, AZ); Thomas I. Sounart (Chandler, AZ); Marcel A. Wall (Phoenix, AZ)
Assignee: Intel Corporation
H01L23/49822H01G4/33H01L21/486H05K1/111H05K1/115H05K1/16H05K1/18H05K1/182H01G4/306H05K1/0231
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,476,175
App. No.
17/485,039
Granted
Nov 18, 2025
Kind
B2
Abstract

Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

Claims (28)

1 . A semiconductor package comprising:

a glass substrate having a through glass via, the through glass via having a length extending between a first surface of the glass substrate and a second surface of the glass substrate opposite the first surface; and

a transverse capacitor located in the through glass via, the transverse capacitor including:

a dielectric material in a first portion of the length of the through glass via, the dielectric material absent from second and third portions of the length of the through glass via, the second portion distinct from the first portion, the third portion distinct from the first portion and distinct from the second portion;

a first barrier layer in the second portion of the length of the through glass via, the first barrier layer absent from the first and third portions; and

a first conductive material in a third portion of the length of the through glass via, the first conductive material absent from the first and second portions.

2 . The semiconductor package of claim 1 , wherein the first barrier layer is between the dielectric material and the first conductive material.

3 . The semiconductor package of claim 2 , wherein the first conductive material is between the second surface of the glass substrate and the first barrier layer.

4 . The semiconductor package of claim 3 , wherein the dielectric material is between the first surface of the glass substrate and the first barrier layer.

5 . The semiconductor package of claim 4 , wherein the dielectric material includes a first side and a second side opposite the first side, wherein the first side is flush relative to the first surface of the glass substrate and the second side is oriented toward the first barrier layer.

6 . The semiconductor package of claim 5 , wherein the second side of the dielectric material directly engages the first barrier layer.

7 . The semiconductor package of claim 4 , wherein the dielectric material includes a first side and a second side opposite the first side, and the first side and the second side are located inside the through glass via.

8 . The semiconductor package of claim 7 , further including a second barrier layer in a fourth portion of the length of the through glass via such that the dielectric material is between the first barrier layer and the second barrier layer.

9 . The semiconductor package of claim 8 , wherein the first side of the dielectric material directly engages the first barrier layer and the second side of the dielectric material directly engages the second barrier layer.

10 . The semiconductor package of claim 1 , wherein the dielectric material spans a diameter of the through glass via.

11 . The semiconductor package of claim 1 , wherein the dielectric material is in contact with a side wall of the through glass via, the first barrier layer is in contact with the side wall of the through glass via, and the first conductive material is in contact with the side wall of the through glass via.

12 . A semiconductor package comprising:

a glass substrate having a first surface, a second surface, and a through glass via extending between the first and second surfaces;

a structure provided in the through glass via, the structure including:

a first conductive material;

a first layer different from the first conductive material, the first conductive material closer to a first end of the through glass via than the first layer is to the first end of the through glass via;

a second conductive material different from the first layer, the second conductive material in a cavity defined by the first layer, the first layer closer to the first end of the through glass via than the second conductive material is to the first end of the through glass via; and

a dielectric material directly on at least one of the first layer or the second conductive material, both the first layer and the second conductive material closer to the first end of the through glass via than the dielectric material is to the first end of the through glass via.

13 . The semiconductor package of claim 12 , wherein the dielectric material has a first end directly engaged with the first layer and a second end flush with the first surface of the glass substrate.

14 . The semiconductor package of claim 12 , wherein the dielectric material has a first end directly engaged with the first layer and a second end recessed from the first surface and positioned inside the through glass via.

15 . The semiconductor package of claim 14 , further including a third layer including a conductive material and a fourth layer including titanium located inside the through glass via and directly on the second end of the dielectric material.

16 . The semiconductor package of claim 12 , including a second layer adjacent the first layer, the second layer including titanium.

17 . The semiconductor package of claim 12 , wherein the dielectric material is closer to a second end of the through glass via than the first layer is to the second end of the through glass via and the dielectric material is closer to the second end of the through glass via than the second conductive material is to the second end of the through glass via.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076064/0951 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2023
From: DUONG, BENJAMIN T.; ALEKSOV, ALEKSANDAR; TORRE, HELME CASTRO DE LA; DARMAWIKARTA, KRISTOF; GRUJICIC, DARKO; KANDANUR, SASHI S.; NAD, SUDDHASATTWA; PIETAMBARAM, SRINIVAS V.; SHANMUGAM, RENGARAJAN; SOUNART, THOMAS I.; WALL, MARCEL A.
To: INTEL CORPORATION
Reel/Frame 063117/0763 →
Continuity (1)
Related Publication 20230095846A1 · Mar 30, 2023
References Cited (4)
US 9391015B2 · Jeannot · 2016 [cited by examiner]
US 20140144681A1 · Pushparaj · 2014 [cited by examiner]
US 20150043126A1 · Hurwitz · 2015 [cited by examiner]
US 20200395435A1 · Haratipour · 2020 [cited by examiner]