IP Library Granted Patent US 12,604,748
Granted Patent B2
US 12,604,748 · App. 17/448,288 · Granted Apr 14, 2026

Capacitor pads and methods of manufacturing the same

Inventors: Kristof Darmawikarta (Chandler, AZ); Jung Kyu Han (Chandler, AZ); Srinivas Pietambaram (Chandler, AZ); Rajeev Ranjan (Chandler, AZ)
Assignee: Intel Corporation
H01L23/49838H01L21/4853H10D1/68H01L23/49816H01L25/16
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Quick Facts
Patent No.
US 12,604,748
App. No.
17/448,288
Granted
Apr 14, 2026
Kind
B2
Abstract

Capacitor pads and methods of manufacturing the same are disclosed herein. An example apparatus disclosed herein includes a substrate to support a die, and a die-side capacitor pad on the substrate, the die-side capacitor pad including a plurality of distinct pad portions, the distinct pad portions spaced apart from one another.

Claims (25)

1 . An apparatus comprising:

a substrate to support a die; and

a die-side capacitor pad on the substrate, the die-side capacitor pad including:

a plurality of distinct pad portions, the distinct pad portions spaced apart from one another; and

a frame around the plurality of the distinct pad portions, the frame to retain solder material associated with a die-side capacitor, the frame flush with at least one of the distinct pad portions.

2 . The apparatus of claim 1 , wherein different ones of the distinct pad portions have a same size and a same shape.

3 . The apparatus of claim 1 , wherein the distinct pad portions include a first pad portion, the first pad portion having a cylindrical shape.

4 . The apparatus of claim 1 , wherein the distinct pad portions include a first pad portion, the first pad portion having a rectangular prism shape.

5 . The apparatus of claim 1 , including a second pad on the substrate, the second pad to bond with a corresponding bump or pad on the die, the second pad having a first size associated with a first cross-sectional area, each of the distinct pad portions having a second size associated with a second cross-sectional area, the second cross-sectional area being less than or equal to the first cross-sectional area.

6 . The apparatus of claim 1 , wherein the frame includes a conductive material.

7 . An apparatus comprising:

a substrate to support a die;

a capacitor including a terminal;

an interconnect extending between the capacitor and the substrate, the interconnect including a first pad on a side of the substrate, the first pad electrically coupling the die to the terminal, the first pad including a plurality of distinct pad portions, each of the distinct pad portions bonded to the terminal of the capacitor; and

a second pad on the side of the substrate, the second pad to electrically couple the substrate to the die, a cross-sectional area of individual ones of the distinct pad portions being less than or equal to a cross-sectional area of the second pad.

8 . The apparatus of claim 7 , wherein the first pad includes a frame around the plurality of the distinct pad portions, the frame to retain solder material that provides the bond between the terminal and each of the distinct pad portions.

9 . The apparatus of claim 8 , wherein the frame is electrically coupled to at least one of the distinct pad portions.

10 . The apparatus of claim 8 , wherein the frame includes a conductive material.

11 . The apparatus of claim 8 , wherein the frame is electrically coupled to the terminal and the die.

12 . The apparatus of claim 7 , wherein different ones of the distinct pad portions have a same size and a same shape.

13 . The apparatus of claim 7 , wherein the distinct pad portions include a first pad portion, the first pad portion having a cylindrical shape.

14 . The apparatus of claim 7 , wherein the distinct pad portions include a first pad portion, the first pad portion having a triangular shape.

15 . The apparatus of claim 7 , wherein the first pad is a capacitor pad and the second pad is a bridge pad.

16 . The apparatus of claim 7 , including a first solder layer on the first pad and a second solder layer on the second pad.

17 . The apparatus of claim 16 , wherein the first solder layer and the second solder layer have a same thickness.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076064/0951 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2022
From: DARMAWIKARTA, KRISTOF; PIETAMBARAM, SRINIVAS; HAN, JUNG KYU; RANJAN, RAJEEV
To: INTEL CORPORATION
Reel/Frame 059036/0374 →
Continuity (1)
Related Publication 20230085698A1 · Mar 23, 2023
References Cited (5)
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US 6387753B1 · Clark · 2002 [cited by examiner]
US 20140376195A1 · Zhang · 2014 [cited by examiner]
US 20190006264A1 · Vaidya · 2019 [cited by examiner]