IP Library › Granted Patent US 12,183,660
Granted Patent B2
US 12,183,660 · App. 17/736,212 · Granted Dec 31, 2024

Semiconductor device including through-silicon via and method of forming the same

Inventors: Jeonil Lee (Suwon-si, KR); Jongmin Lee (Hwaseong-si, KR); Jimin Choi (Seoul, KR); Yeonjin Lee (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L23/481H01L21/76895H01L21/76898H01L23/53228H01L23/53257H01L23/535
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,183,660
App. No.
17/736,212
Granted
Dec 31, 2024
Kind
B2
Abstract

A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

Claims (49)

1. A semiconductor device comprising:

a substrate comprising a first surface and a second surface opposing the first surface;

a via insulating layer extending through the substrate;

a through-silicon via extending through the via insulating layer, a center of the through-silicon via misaligned from a center of the via insulating layer;

a blocking layer on the first surface;

a first insulating layer on the blocking layer; and

a contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer.

2. The semiconductor device according to claim 1 , wherein,

the through-silicon via comprises a first side surface and a second side surface opposing the first side surface,

the via insulating layer comprises a first portion adjacent to the first side surface, and a second portion adjacent to the second side surface, and

a first horizontal width of the first portion is greater than a second horizontal width of the second portion.

3. The semiconductor device according to claim 1 , wherein a distance between a lowermost end of the contact plug and the second surface is less than or equal to a distance between the first surface and the second surface.

4. The semiconductor device according to claim 1 , wherein a distance between a lowermost end of the contact plug and the second surface is less than or equal to a distance between an uppermost end of the via insulating layer and the second surface.

5. The semiconductor device according to claim 1 , wherein the via insulating layer has a width relatively increasing as the via insulating layer extends toward the first surface, and the via insulating layer has a width relatively decreasing as the via insulating layer extends toward the second surface.

6. The semiconductor device according to claim 1 , wherein the through-silicon via has a width relatively decreasing as the through-silicon via extends toward the first surface, and the through-silicon via has a width relatively increasing as the through-silicon via extends toward the second surface.

7. The semiconductor device according to claim 1 , wherein a horizontal width of the through-silicon via is greater than a horizontal width of the contact plug.

8. The semiconductor device according to claim 1 , wherein the through-silicon via contacts a lower surface and a side surface of the contact plug.

9. The semiconductor device according to claim 1 , wherein the through-silicon via contacts the blocking layer.

10. The semiconductor device according to claim 1 , wherein an uppermost end of the through-silicon via is coplanar with the first surface.

11. The semiconductor device according to claim 1 , wherein the blocking layer extends on the via insulating layer.

12. The semiconductor device according to claim 1 , wherein,

the via insulating layer comprises silicon oxide, and

the blocking layer comprises silicon nitride.

13. The semiconductor device according to claim 1 , wherein:

the contact plug comprises tungsten (W), and

the through-silicon via comprises copper (Cu).

14. The semiconductor device according to claim 1 , further comprising:

a second insulating layer on the first insulating layer; and

a wiring in the second insulating layer and contacting the contact plug,

wherein the wiring comprises copper (Cu).

15. The semiconductor device according to claim 1 , further comprising:

a spacer having a uniform thickness between the through-silicon via and the via insulating layer.

16. A method of forming the semiconductor device of claim 1 , comprising:

forming the via insulating layer extending through the substrate, the forming the via insulating layer comprising performing a first thin film formation process at between 400° C. to 1,300° C.;

forming the contact plug; and

forming the through-silicon via after formation of the via insulating layer and the contact plug.

17. The method according to claim 16 , further comprising:

forming a transistor on the substrate after forming the via insulating layer and before forming the through-silicon via.

18. The method according to claim 16 , further comprising:

forming a spacer between the through-silicon via and the via insulating layer after forming the via insulating layer and the contact plug,

wherein the forming the spacer comprises performing a second thin film formation process at a lower temperature than the forming the via insulating layer.

19. The method according to claim 18 , wherein the forming the spacer comprises the second thin film formation process, which is performed at between 150° C. to 400° C.

20. A semiconductor device comprising:

a substrate comprising a first surface and a second surface opposing the first surface;

a via insulating layer extending through the substrate, the via insulating layer having a width relatively increasing as the via insulating layer extends toward the first surface and having a width relatively decreasing as the via insulating layer extends toward the second surface;

a through-silicon via extending through the via insulating layer, the through-silicon via having a width relatively decreasing as the through-silicon via extends toward the first surface and having a width relatively increasing as the through-silicon via extends toward the second surface;

a blocking layer on the first surface;

a first insulating layer on the blocking layer; and

a contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2022
From: LEE, JEONIL; LEE, JONGMIN; CHOI, JIMIN; LEE, YEONJIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 059837/0264 →
Priority Claims (1)
KR 10-2021-0135450 · Oct 13, 2021 · national
Continuity (1)
Related Publication 20230116911A1 · Apr 13, 2023