Semiconductor device
A semiconductor device is provided. The semiconductor device includes: lower nanosheets; upper nanosheets on the lower nanosheets; gate electrodes on the substrate and provided around each of the nanosheets; a first lower source/drain region on a first side of the first and second gate electrodes; a second lower source/drain region on a second side of the first and second gate electrodes; a first upper source/drain region on the first lower source/drain region; and a second upper source/drain region on the second lower source/drain region. A first length of the second lower source/drain region is greater than a second length of the second upper source/drain region.
1 . A semiconductor device comprising:
a substrate;
a plurality of lower nanosheets on the substrate and extending in a first horizontal direction, wherein the plurality of lower nanosheets are stacked and spaced apart from each other in a vertical direction;
a plurality of upper nanosheets on the plurality of lower nanosheets and extending in the first horizontal direction, wherein the plurality of upper nanosheets are stacked and spaced apart from each other in the vertical direction;
first to fourth gate electrodes on the substrate and extending in a second horizontal direction different from the first horizontal direction, wherein the first to fourth gate electrodes are provided around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets, the second gate electrode is spaced apart from the first gate electrode in the second horizontal direction, the third gate electrode is spaced apart from the first gate electrode in the first horizontal direction, and the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction;
a first lower source/drain region on a first side of the first and second gate electrodes;
a second lower source/drain region on a second side of the first and second gate electrodes opposite to the first side in the first horizontal direction, wherein the second side of the first and second gate electrodes faces the third and fourth gate electrodes;
a first upper source/drain region on the first lower source/drain region;
a second upper source/drain region on the second lower source/drain region,
a buried contact connected to the first lower source/drain region; and
an interlayer insulating layer between the first lower source/drain region and the first upper source/drain region, and between the second lower source/drain region and the second upper source/drain region,
wherein a first length in the second horizontal direction of the second lower source/drain region is greater than a second length in the second horizontal direction of the second upper source/drain region,
wherein the first lower source/drain region comprises a third lower source/drain region on the first side of the first gate electrode and a fourth lower source/drain region on the first side of the second gate electrode, and
wherein the buried contact extends between the third lower source/drain region and the fourth lower source/drain region.
2 . The semiconductor device of claim 1 ,
wherein the second lower source/drain region comprises a fifth lower source/drain region on the second side of the first gate electrode, and a sixth lower source/drain region on the second side of the second gate electrode,
wherein the fourth lower source/drain region is spaced apart from the third lower source/drain region in the second horizontal direction, and
wherein the sixth lower source/drain region is spaced apart from the fifth lower source/drain region in the second horizontal direction.
3 . The semiconductor device of claim 2 ,
wherein the buried contact is electrically connected to each of the third and fourth lower source/drain regions, and the buried contact extends into an inside of the substrate.
4 . The semiconductor device of claim 3 , wherein at least a portion of the buried contact does not overlap the first lower source/drain region in the second horizontal direction.
5 . The semiconductor device of claim 2 , further comprising:
a first lower source/drain contact on the second side of the first gate electrode, and electrically connected to the fifth lower source/drain region; and
a second lower source/drain contact on the second side of the second gate electrode, and electrically connected to the sixth lower source/drain region,
wherein the first and second lower source/drain contacts are spaced apart from the second upper source/drain region.
6 . The semiconductor device of claim 1 , wherein the first upper source/drain region comprises a third upper source/drain region on the first side of the first gate electrode and a fourth upper source/drain region on the first side of the second gate electrode,
wherein the second upper source/drain region comprises a fifth upper source/drain region on the second side of the first gate electrode and a sixth upper source/drain region on the second side of the second gate electrode,
wherein the fourth upper source/drain region is spaced apart from the third upper source/drain region in the second horizontal direction, and
wherein the sixth upper source/drain region is spaced apart from the fifth upper source/drain region in the second horizontal direction.
7 . The semiconductor device of claim 6 , further comprising:
a first upper source/drain contact on the first side of the first and second gate electrodes, and electrically connected to each of the third and fourth upper source/drain regions; and
a second upper source/drain contact on the second side of the first and second gate electrodes, and electrically connected to each of the fifth and sixth upper source/drain regions.
8 . The semiconductor device of claim 1 , wherein the first length is shorter than three times of the second length.
9 . The semiconductor device of claim 1 , wherein the plurality of lower nanosheets are in an NMOS region, and the plurality of upper nanosheets are in a PMOS region.
10 . A semiconductor device comprising:
a substrate;
a plurality of lower nanosheets on the substrate and extending in a first horizontal direction, wherein the plurality of lower nanosheets are stacked and spaced apart from each other in a vertical direction;
a plurality of upper nanosheets on the plurality of lower nanosheets and extending in the first horizontal direction, wherein the plurality of upper nanosheets are stacked and spaced apart from each other in the vertical direction;
a first gate electrode on the substrate and extending in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode is provided around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets;
a second gate electrode on the substrate and extending in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the second horizontal direction, and the second gate electrode is provided around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets;
a lower source/drain region on first and second sides of the first and second gate electrodes;
an upper source/drain region on the lower source/drain region on the first and second sides of the first and second gate electrodes;
a buried contact connected to the lower source/drain region; and
an interlayer insulating layer between the lower source/drain region and the upper source/drain region,
wherein on at least one side of the first and second sides of the first and second gate electrodes, a first length in the second horizontal direction of the lower source/drain region is greater than a second length in the second horizontal direction of the upper source/drain region,
wherein the lower source/drain region comprises a first lower source/drain region on the first side of the first gate electrode and a second lower source/drain region on the first side of the second gate electrode, and
wherein the buried contact extends between the first lower source/drain region and the second lower source/drain region.
11 . The semiconductor device of claim 10 , further comprising:
a third gate electrode on the substrate and extending in the second horizontal direction, wherein the third gate electrode is spaced apart from the first gate electrode in the first horizontal direction; and
a fourth gate electrode on the substrate and extending in the second horizontal direction, wherein the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction,
wherein the at least one side is between the first and third gate electrodes, and between the second and fourth gate electrodes.
12 . The semiconductor device of claim 10 ,
wherein the buried contact extends between the first lower source/drain region and the second lower source/drain region, wherein the buried contact is electrically connected to each of the first and second lower source/drain regions, and the buried contact extends into an inside of the substrate.
13 . The semiconductor device of claim 10 , further comprising:
a third gate electrode on the substrate and extending in the second horizontal direction, wherein the third gate electrode is spaced apart from the second gate electrode in the second horizontal direction; and
a fourth gate electrode on the substrate and extending in the second horizontal direction, wherein the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction.
14 . The semiconductor device of claim 10 ,
wherein the lower source/drain region comprises a third lower source/drain region on the second side of the first and second gate electrodes,
wherein the upper source/drain region comprises:
a first upper source/drain region on the first lower source/drain region; and
a third upper source/drain region on the third lower source/drain region,
wherein the first length in the second horizontal direction of the first lower source/drain region is greater than the second length in the second horizontal direction of the first upper source/drain region, and
wherein a third length in the second horizontal direction of the third lower source/drain region is greater than a fourth length in the second horizontal direction of the third upper source/drain region.
15 . A semiconductor device comprising:
a substrate;
a plurality of lower nanosheets on the substrate and extending in a first horizontal direction, wherein the plurality of lower nanosheets are stacked and spaced apart from each other in a vertical direction;
a plurality of upper nanosheets on the plurality of lower nanosheets and extending in the first horizontal direction, the plurality of upper nanosheets are stacked and spaced apart from each other in the vertical direction;
a first gate electrode on the substrate and extending in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode is provided around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets;
a second gate electrode on the substrate and extending in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the second horizontal direction, and the second gate electrode is provided around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets;
a first lower source/drain region on a first side of the first and second gate electrodes;
a second lower source/drain region on a second side of the first and second gate electrodes opposite to the first side in the first horizontal direction;
a first upper source/drain region on the first lower source/drain region;
a second upper source/drain region on the second lower source/drain region;
an interlayer insulating layer between the first lower source/drain region and the first upper source/drain region, and between the second lower source/drain region and the second upper source/drain region; and
a buried contact electrically connected to a lower source/drain region of the first and second lower source/drain regions and extending between portions of the lower/source drain region into an inside of the substrate.
16 . The semiconductor device of claim 15 , further comprising:
a third gate electrode on the substrate and extending in the second horizontal direction, wherein the third gate electrode is spaced apart from the first gate electrode in the first horizontal direction; and
a fourth gate electrode on the substrate and extending in the second horizontal direction, wherein the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction.
17 . The semiconductor device of claim 16 , wherein between the first and third gate electrodes, and between the second and fourth gate electrodes, a first length in the second horizontal direction of the second lower source/drain region is greater than a second length in the second horizontal direction of the second upper source/drain region.
18 . The semiconductor device of claim 15 , further comprising:
a third gate electrode on the substrate and extending in the second horizontal direction, wherein the third gate electrode is spaced apart from the second gate electrode in the second horizontal direction; and
a fourth gate electrode on the substrate and extending in the second horizontal direction, wherein the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction.
19 . The semiconductor device of claim 18 , wherein on the first side of the first and second gate electrodes, a third length in the second horizontal direction of the first lower source/drain region is greater than a fourth length in the second horizontal direction of the first upper source/drain region.
20 . The semiconductor device of claim 15 , wherein the buried contact comprises:
a first buried contact electrically connected to the first lower source/drain region, and extending into the inside of the substrate; and
a second buried contact electrically connected to the second lower source/drain region, and extending into the inside of the substrate.