Semiconductor package
A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.
1. A semiconductor package comprising:
a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads;
a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate;
a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate;
a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core ball; and
a plurality of solder balls of which at least some vertically overlap the plurality of second upper surface pads, the plurality of solder balls connecting others of the plurality of first upper surface pads to others of the plurality of second lower surface pads,
wherein each of the plurality of metal core structures includes the metal core ball and a solder layer surrounding the metal core ball.
2. The semiconductor package of claim 1 , wherein a maximum horizontal width of each of the plurality of metal core structures is greater than a maximum horizontal width of each of the plurality of solder balls.
3. The semiconductor package of claim 1 , wherein the metal core ball has a spherical shape having a maximum horizontal width equal to a maximum vertical height.
4. The semiconductor package of claim 1 , wherein the metal core ball has a rugby ball shape having a maximum vertical height greater than a maximum horizontal width.
5. The semiconductor package of claim 1 , wherein the plurality of metal core structures are arranged to have point symmetry with respect to a center of the first package substrate in a plan view.
6. The semiconductor package of claim 5 , wherein two opposite edges of the first package substrate and two opposite edges of the semiconductor chip corresponding thereto are isolated from each other by a first distance in the plan view, and two other opposite edges of the first package substrate and two other opposite edges of the semiconductor chip corresponding thereto are isolated from each other by a second distance less than the first distance in the plan view, and
wherein the plurality of metal core structures are between the two opposite edges of the first package substrate and the two opposite edges of the semiconductor chip corresponding thereto.
7. The semiconductor package of claim 1 , wherein the plurality of metal core structures form a plurality of core structure groups, each group respectively including at least two of the metal core structures, and
wherein the plurality of core structure groups are arranged to have point symmetry with respect to a central portion of the first package substrate in a plan view.
8. The semiconductor package of claim 1 , further comprising:
an upper package including a plurality of package connection members attached to at least some of the plurality of second upper surface pads, and an upper semiconductor chip electrically connected to the plurality of package connection members.
9. A semiconductor package comprising:
a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads;
a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate;
a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate;
a plurality of metal core structures and a plurality of solder balls, separate from each other, connected between the plurality of first upper surface pads and the plurality of second lower surface pads, and arranged around the semiconductor chip to be isolated from the semiconductor chip in a plan view; and
an encapsulant filling a space between the first package substrate and the second package substrate, and encapsulating the semiconductor chip, the plurality of metal core structures, and the plurality of solder balls,
wherein the plurality of metal core structures do not vertically overlap any of the plurality of second upper surface pads, and
wherein at least some of the plurality of solder balls vertically overlap some of the plurality of second upper surface pads, respectively, and others of the plurality of solder balls do not vertically overlap any of the plurality of second upper surface pads.
10. The semiconductor package of claim 9 , wherein a vertical height of each of the plurality of metal core structures is equal to a vertical height of each of the plurality of solder balls, and
wherein a maximum horizontal width of each of the plurality of metal core structures is equal to a maximum horizontal width of each of the plurality of solder balls.
11. The semiconductor package of claim 9 , wherein each of the plurality of metal core structures includes a metal core ball having a spherical shape, and a barrier layer conformally covering a surface of the metal core ball, wherein the solder layer surrounds the barrier layer.
12. The semiconductor package of claim 9 , wherein the plurality of metal core structures form a plurality of core structure groups, each respectively including at least two of the metal core structures, and
wherein the plurality of core structure groups are arranged to have point symmetry with respect to a center of the first package substrate in a plan view.
13. The semiconductor package of claim 12 , wherein the plurality of core structure groups are arranged between two opposite edges of the first package substrate and two opposite edges of the semiconductor chip corresponding thereto in a plan view, and are not arranged between two other opposite edges of the first package substrate and two other opposite edges of the semiconductor chip corresponding thereto.
14. The semiconductor package of claim 13 , wherein a distance between the two opposite edges of the first package substrate and the two opposite edges of the semiconductor chip corresponding thereto is greater than a distance between the two other opposite edges of the first package substrate and the two other opposite edges of the semiconductor chip corresponding thereto.
15. A semiconductor package comprising:
a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads;
a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads;
a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate;
an encapsulant filling a space between the first package substrate and the second package substrate and surrounding the semiconductor chip; and
a plurality of metal core structures and a plurality of solder balls, separate from each other, passing through the encapsulant to connect the plurality of first upper surface pads to the plurality of second lower surface pads, and arranged around the semiconductor chip to be isolated from the semiconductor chip in a plan view,
wherein the plurality of metal core structures each include a metal core ball not including solder,
wherein the plurality of metal core structures are arranged to have point symmetry with respect to a central portion of the first package substrate in a plan view and do not vertically overlap the plurality of second upper surface pads, and
wherein at least some of the plurality of solder balls vertically overlap the plurality of second upper surface pads, and others of the plurality of solder balls do not overlap the plurality of second upper surface pads.
16. The semiconductor package of claim 15 , wherein each of the plurality of metal core structures includes the metal core ball having a spherical shape, a solder layer surrounding the metal core ball, and a barrier layer between the metal core ball and the solder layer,
wherein a vertical height of each of the plurality of metal core structures is equal to a vertical height of each of the plurality of solder balls, and
wherein a maximum horizontal width each metal core structure is a width from about 100 μm to about 400 μm, and a maximum horizontal width of each solder ball is smaller than the maximum horizontal width of each metal core structure, and is from about 55 μm to about 220 μm.
17. The semiconductor package of claim 16 , wherein the metal core ball includes copper (Cu), and
wherein the solder layer and the plurality of solder balls are formed of conductive solder.
18. The semiconductor package of claim 9 , wherein each of the plurality of metal core structures includes a metal core and a solder layer surrounding the metal core.