IP Library › Granted Patent US 12,414,481
Granted Patent B2
US 12,414,481 · App. 17/743,459 · Granted Sep 9, 2025

Semiconductor device and method for fabricating the same

Inventors: Jia-Rong Wu (Kaohsiung, TW); Chi-Hsuan Cheng (Kaohsiung, TW); Rai-Min Huang (Taipei, TW); Po-Kai Hsu (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N52/01H10B61/00H10N52/00H10N52/80
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Quick Facts
Patent No.
US 12,414,481
App. No.
17/743,459
Granted
Sep 9, 2025
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the first SOT layer, forming a second SOT layer on the IMD layer, forming a first hard mask on the second SOT layer, patterning the first hard mask along a first direction, and then patterning the first hard mask along a second direction.

Claims (19)

1. A method for fabricating a semiconductor device, comprising:

forming a magnetic tunneling junction (MTJ) on a substrate;

forming a first spin orbit torque (SOT) layer on the MTJ;

forming an inter-metal dielectric (IMD) layer around the first SOT layer;

forming a second SOT layer on the IMD layer;

forming a first hard mask on the second SOT layer;

forming a third hard mask on the second SOT layer;

patterning the first hard mask along a first direction for forming a first opening;

patterning the first hard mask along a second direction after patterning the first hard mask along the first direction for forming a second opening; and

etching the third hard mask and the second SOT layer through the first opening and the second opening.

2. The method of claim 1 , further comprising:

forming a second hard mask on the first SOT layer;

forming a spacer adjacent to the first SOT layer;

forming the IMD layer around the spacer; and

forming the second SOT layer on the first SOT layer, the spacer, and the IMD layer.

3. The method of claim 2 , wherein the second hard mask comprises ruthenium (Ru).

4. The method of claim 2 , wherein the third hard mask comprises metal.

5. The method of claim 2 , wherein the top surfaces of the second hard mask and the IMD layer are coplanar.

6. The method of claim 1 , wherein the first direction is orthogonal to the second direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2022
From: WU, JIA-RONG; CHENG, CHI-HSUAN; HUANG, RAI-MIN; HSU, PO-KAI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 059896/0756 →
Priority Claims (1)
CN 202210397417.0 · Apr 15, 2022 · national
Continuity (1)
Related Publication 20230337551A1 · Oct 19, 2023
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