Inline circuit edit for backside power delivery with deep via
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.
1 . An integrated circuit structure, comprising:
a device layer comprising a plurality of transistor structures, the plurality of transistor structures comprising a first stack of nanowires surrounded by a first gate electrode, and a second stack of nanowires surrounded by a second gate electrode;
a front-end routing layer above the device layer, the front-end routing layer coupled to one or more of the plurality of transistor structures;
a backside metal structure below the device layer; and
a conductive feedthrough structure directly coupling the backside metal structure to the front-end routing layer, the conductive feedthrough structure laterally between the first stack of nanowires and the second first stack of nanowires, and the conductive feedthrough structure extending above the first gate electrode and the second gate electrode.
2 . The integrated circuit structure of claim 1 , further comprising a second backside metal structure coupled to an epitaxial source or drain structure of one of the plurality of transistors, the second backside metal structure laterally adjacent to the backside metal structure.
3 . The integrated circuit structure of claim 1 , further comprising a backside routing layer below the backside metal structure.
4 . The integrated circuit structure of claim 1 , wherein the conductive feedthrough structure delivers power from the backside metal structure to the front-end routing layer.
5 . The integrated circuit structure of claim 1 , wherein access to the conductive feedthrough structure by the backside metal structure is enabled using an inline circuit edit process.
6 . A method of fabricating an integrated circuit structure, the method comprising:
forming a device layer comprising a plurality of transistor structures, the plurality of transistor structures comprising a first stack of nanowires surrounded by a first gate electrode, and a second stack of nanowires surrounded by a second gate electrode;
forming a front-end routing layer above the device layer, the front-end routing layer coupled to one or more of the plurality of transistor structures;
accessing a backside of a front-end-fabricated conductive feedthrough structure using a maskless lithography process, the conductive feedthrough structure coupled to the front-end routing layer, the conductive feedthrough structure laterally between the first stack of nanowires and the second first stack of nanowires, and the conductive feedthrough structure extending above the first gate electrode and the second gate electrode;
forming a backside metal structure using a masked lithography process, the backside metal structure coupled to one of the plurality of transistors.
7 . The method of claim 6 , further comprising forming a second backside metal structure below the device layer, wherein the conductive feedthrough structure directly couples the second backside metal structure to the front-end routing layer.
8 . The method of claim 7 , wherein the maskless lithography process is an e-beam process.
9 . The method of claim 7 , wherein the masked lithography process is an extreme ultraviolet (EUV) process.
10 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a device layer comprising a plurality of transistor structures, the plurality of transistor structures comprising a first stack of nanowires surrounded by a first gate electrode, and a second stack of nanowires surrounded by a second gate electrode;
a front-end routing layer above the device layer, the front-end routing layer coupled to one or more of the plurality of transistor structures;
a backside metal structure below the device layer; and
a conductive feedthrough structure directly coupling the backside metal structure to the front-end routing layer, the conductive feedthrough structure laterally between the first stack of nanowires and the second first stack of nanowires, and the conductive feedthrough structure extending above the first gate electrode and the second gate electrode.
11 . The computing device of claim 10 , further comprising:
a memory coupled to the board.
12 . The computing device of claim 10 , further comprising:
a communication chip coupled to the board.
13 . The computing device of claim 10 , wherein the component is a packaged integrated circuit die.
14 . The computing device of claim 10 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
15 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure fabricated according to a method comprising:
forming a device layer comprising a plurality of transistor structures, the plurality of transistor structures comprising a first stack of nanowires surrounded by a first gate electrode, and a second stack of nanowires surrounded by a second gate electrode;
forming a front-end routing layer above the device layer, the front-end routing layer coupled to one or more of the plurality of transistor structures;
accessing a backside of a front-end-fabricated conductive feedthrough structure using a maskless lithography process, the conductive feedthrough structure coupled to the front-end routing layer, the conductive feedthrough structure laterally between the first stack of nanowires and the second first stack of nanowires, and the conductive feedthrough structure extending above the first gate electrode and the second gate electrode;
forming a backside metal structure using a masked lithography process, the backside metal structure coupled to one of the plurality of transistors.
16 . The computing device of claim 15 , further comprising:
a memory coupled to the board.
17 . The computing device of claim 15 , further comprising:
a communication chip coupled to the board.
18 . The computing device of claim 15 , wherein the component is a packaged integrated circuit die.
19 . The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.