IP Library Granted Patent US 12,382,663
Granted Patent B2
US 12,382,663 · App. 17/745,953 · Granted Aug 5, 2025

Semiconductor device having metal oxide layer with tapered side surface

Inventors: Toshiki Kaneko (Tokyo, JP); Fumiya Kimura (Tokyo, JP)
Assignee: MAGNOLIA WHITE CORPORATION
H10D30/6739H10D64/01H10D99/00H10D30/6723H10D30/6755H10D30/6758
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Quick Facts
Patent No.
US 12,382,663
App. No.
17/745,953
Granted
Aug 5, 2025
Kind
B2
Abstract

A semiconductor device includes a substrate, an oxide semiconductor layer over the substrate, a gate insulating layer over the oxide semiconductor layer, a metal oxide layer over the gate insulating layer, and a gate electrode over the metal oxide layer. A first side surface of the metal oxide protrudes from a second side surface of the gate electrode in a plan view.

Claims (19)

1. A semiconductor device comprising:

a substrate;

an oxide semiconductor layer over the substrate;

a gate insulating layer over the oxide semiconductor layer;

a metal oxide layer over the gate insulating layer; and

a gate electrode over the metal oxide layer,

wherein a first side surface of the metal oxide protrudes from a second side surface of the gate electrode in a plan view, and

wherein a first taper angle between the first side surface and a lower surface of the metal oxide layer is smaller than a second taper angle between the second side surface and a lower surface of the gate electrode.

2. The semiconductor device according to claim 1 , wherein the first taper angle is greater than or equal to 30 degrees and less than or equal to 70 degrees.

3. The semiconductor device according to claim 1 , wherein a thickness of the metal oxide layer is greater than or equal to 10 nm and less than or equal to 100 nm.

4. The semiconductor device according to claim 1 , wherein the metal oxide layer comprises indium.

5. The semiconductor device according to claim 1 ,

wherein the gate electrode comprises:

a first metal layer in contact with the metal oxide layer; and

a second metal layer over the first metal layer, and

the second metal layer comprises aluminum.

6. The semiconductor device according to claim 5 , wherein the first metal layer comprises molybdenum.

7. The semiconductor device according to claim 1 , wherein a side surface of the oxide semiconductor layer is covered with the gate insulating layer.

8. The semiconductor device according to claim 1 , wherein the substrate is a flexible substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 071599/0406 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2022
From: KANEKO, TOSHIKI; KIMURA, FUMIYA
To: JAPAN DISPLAY INC.
Reel/Frame 060081/0383 →
Priority Claims (1)
JP 2021-084709 · May 19, 2021 · national
Continuity (1)
Related Publication 20220376076A1 · Nov 24, 2022
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