Circuit design having an improved clock tree
A system and method updates a clock tree based on skew values of the circuit design. The clock tree is updated by obtaining a circuit design that includes circuit elements and a clock tree. The clock tree includes clock sources and clock sinks. Data path slack values for the clock tree are determined based on the clock sources and the clock sinks. Further, clock arrival values for the clock tree are determined based on the clock sources and the clock sinks. A first total local skew value of the circuit design is determined based on the data path slack values, and the clock arrival values, and updating the clock tree based on the first total local skew value.
1. A method comprising:
obtaining a circuit design including circuit elements and a clock tree, the clock tree including clock sources and clock sinks;
determining data path slack values for the clock tree based on the clock sources and the clock sinks;
determining clock arrival values for the clock tree based on the clock sources and the clock sinks;
determining, by a processing device, a first total local skew value of the circuit design based on the data path slack values, and the clock arrival values; and
updating the clock tree based on the first total local skew value.
2. The method of claim 1 , wherein determining the data path slack values comprises determining a data path slack value for each clock source and clock sink pair, wherein each clock source and clock sink pair includes a clock source of the clock sources and a clock sink of the clock sinks.
3. The method of claim 2 , wherein determining the data path slack value for each clock source and clock sink pair comprises tracing a timing path between the clock source and the clock sink in each clock source and clock sink pair.
4. The method of claim 1 , wherein determining the clock arrival values includes traversing the clock tree from each of the clock sources to each of the clock sinks.
5. The method of claim 1 , wherein the first total local skew value of the circuit design is further based on a smoothing factor.
6. The method of claim 5 , further comprising:
reducing the smoothing factor to generate a reduced smoothing factor; and
determining a second total local skew value of the circuit design based on the reduced smoothing factor.
7. The method of claim 1 , wherein updating the clock tree based on the first total local skew value comprises at least one of:
inserting one or more buffers within the clock tree based on the first total local skew value; or
adjusting a gate size of the circuit design based on the first total local skew value.
8. A system comprising:
a memory storing instructions; and
a processor, coupled with the memory and configured to execute the instructions, the instructions when executed cause the processor to:
obtain a circuit design including circuit elements and a clock tree, the clock tree including clock sources and clock sinks;
determine data path slack values for the clock tree based on the clock sources and the clock sinks;
determine clock arrival values for the clock tree based on the clock sources and the clock sinks;
determine a first total local skew value of the circuit design based on the data path slack values, and the clock arrival values; and
update the clock tree based on the first total local skew value.
9. The system of claim 8 , wherein determining the data path slack values comprises determining a data path slack value of the data path slack values for each clock source and clock sink pair, wherein each clock source and clock sink pair includes a clock source of the clock sources and a clock sink of the clock sinks.
10. The system of claim 9 , wherein determining the data path slack value for each clock source and clock sink pair comprises tracing a timing path between the clock source and clock sink in each clock source and clock sink pair.
11. The system of claim 8 , wherein determining the clock arrival values includes traversing the clock tree from each of the clock sources to each of the clock sinks.
12. The system of claim 8 , wherein the first total local skew value of the circuit design is further based on a smoothing factor.
13. The system of claim 12 , wherein the processor is further caused to:
reduce the smoothing factor to generate a reduced smoothing factor; and
determine a second total local skew value of the circuit design based on the reduced smoothing factor.
14. The system of claim 8 , wherein updating the clock tree based on the first total local skew value comprises at least one of:
inserting one or more buffers within the circuit design based on the first total local skew value; or
adjusting a gate size of the circuit design based on the first total local skew value.
15. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
obtain a circuit design including circuit elements and a clock tree, the clock tree including clock sources and clock sinks;
determine data path slack values for the clock tree based on the clock sources and the clock sinks;
determine clock arrival values for the clock tree based on the clock sources and the clock sinks; and
update the clock tree by adjusting timings within the clock tree based on the data path slack values and the clock arrival values.
16. The non-transitory computer readable medium of claim 15 , wherein the processor is further caused to determine a first total local skew value of the circuit design based on the data path slack values, the clock arrival values, and a smoothing factor, wherein the adjusting the timings within the clock tree is based on the first total local skew value.
17. The non-transitory computer readable medium of claim 16 , wherein the processor is further caused to:
reduce the smoothing factor to generate a reduced smoothing factor; and
determine a second total local skew value of the circuit design based on the reduced smoothing factor.
18. The non-transitory computer readable medium of claim 15 , wherein determining the data path slack values comprises determining a data path slack value for each clock source and clock sink pair by tracing a timing path between the clock source and clock sink in each clock source and clock sink pair, wherein each clock source and clock sink pair includes one of the clock sources and one of the clock sinks.
19. The non-transitory computer readable medium of claim 15 , wherein determining the clock arrival values includes traversing the clock tree from each of the clock sources to each of the clock sinks.
20. The non-transitory computer readable medium of claim 15 , wherein updating the clock tree comprises at least one of:
inserting one or more buffers within the circuit design based on the data path slack values and the clock arrival values; or
adjusting a gate size of the circuit design based on the data path slack values and the clock arrival values.