Method of measuring the impact of clock skew on slack during a statistical static timing analysis
Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.
1. A method for computing a difference between a measured slack and a zero clock skew slack in presence of statistical sources of variation, comprising:
a) using a computer for performing an initial statistical static timing analysis (SSTA), including a common path pessimism removal (CPPR) analysis;
b) selecting from said SST analysis at least one launching and capturing at least one path-pair for skew analysis; and
c) said skew analysis including calculating said difference between said measured slack and said zero clock skew slack by algebraically adding a post CPPR slack, a total mean latch-to-latch delay, a statistical sum of a latch-to-latch random delay, and a test guard time, and subtracting from said algebraic sum a test adjust value.
2. The method recited in claim 1 further comprising recording said post CPPR slack, said total mean value of latch-to-latch delay, said statistical RSS value of latch to latch delay, said test guard time, and said test adjust occurring during said CPPR analysis.
3. The method recited in claim 2 , wherein determining the impact of said clock skew on said statistical slack is performed during said CPPR analysis.
4. The method as recited in claim 3 , wherein said performing is executed within existing SSTA sign-off flows, facilitating an incremental re-analysis in response to design changes.
5. The method recited in claim 1 , wherein said selected at least one launching and capturing paths pairs are sorted and recorded based on said clock skew impact on downstream slack.
6. The method recited in claim 1 , wherein said path-pairs are sorted and recorded based on statistical criticality.
7. The method as recited in claim 6 , wherein said recorded path-pairs include both said post CPPR slack including RSS credit, and said clock skew impact on the slack.
8. The method recited in claim 1 , further comprises applying to path-pairs gate-level timing, transistor-level timing, hierarchical timing, abstracted timing, timing analysis comprising multiple clock domains, timing analysis comprising phase locked loops , and any combination thereof.
9. The method recited in claim 1 , further applying to path-pairs leading to any test type consisting of: hold, clock gating, pulse width, clock overlap, and end of cycle.
10. The method as recited in claim 1 , further comprising recording said impact of said clock skew on said statistical slack using predetermined timing quantities.
11. A system for computing an exact formulation of clock skew impact on slack in presence of statistical sources of variation, comprising:
a) using a computer for performing an initial statistical static timing analysis (SSTA) including common path pessimism removal (CPPR) analysis;
b) selecting from said SST analysis at least one launch and capturing at least one path-pair for skew analysis; and
c) said skew analysis including computing said exact formulation of said impact of said clock skew contribution to test a slack by algebraically adding a post CPPR slack a total mean latch-to-latch delay, a root-sum square of independently random latch-to-latch delay, and a test guard time, and subtracting from said algebraic sum a test adjust value.
12. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to compute an exact formulation of a clock skew impact on slack in presence of statistical sources of variation, comprising:
a) using a computer for performing an initial statistical static timing analysis (SSTA), including common path pessimism removal (CPPR) analysis;
b) selecting from said SST analysis at least one launch and capturing at least one path-pair for skew analysis; and
c) said skew analysis including calculating said exact formulation of said impact of said clock skew contribution to test a slack by algebraically adding a post CPPR slack, a total mean latch-to-latch delay, a root-sum square of independently random latch-to-latch delay, and a test guard time, and subtracting from said algebraic sum a test adjust value.