IP Library › Granted Patent US 11,837,552
Granted Patent B2
US 11,837,552 · App. 17/748,308 · Granted Dec 5, 2023

Semiconductor package with layer structures, antenna layer and electronic component

Inventors: Wen-Sung Hsu (Hsin-Chu, TW); Tao Cheng (Hsinchu, TW); Nan-Cheng Chen (Hsin-Chu, TW); Che-Ya Chou (Kaohsiung, TW); Wen-Chou Wu (Hsinchu, TW); Yen-Ju Lu (New Taipei, TW); Chih-Ming Hung (McKinney, TX); Wei-Hsiu Hsu (Hsinchu, TW)
Assignee: MediaTek Inc.
H01L23/5389H01L21/486H01L21/4846H01L21/4853H01L21/565H01L21/568H01L21/6835H01L23/3114H01L23/3128H01L23/49811H01L23/49827H01L23/50H01L23/5383H01L23/66H01L25/0657H01L25/10H01L25/105H01L25/16H01L25/162H01L25/165H01L25/50H01Q1/2283H01Q9/0407H01Q9/0414H01L23/145H01L23/49816H01L24/13H01L24/16H01L24/48H01L24/81H01L2221/68345H01L2221/68359H01L2223/6677H01L2224/131H01L2224/13101H01L2224/16225H01L2224/16227H01L2224/16238H01L2224/45099H01L2224/48227H01L2224/81005H01L2225/1023H01L2225/1041H01L2225/1058H01L2924/00014H01L2924/014H01L2924/1533H01L2924/1579H01L2924/15311H01L2924/181H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19106H01Q21/065
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Quick Facts
Patent No.
US 11,837,552
App. No.
17/748,308
Granted
Dec 5, 2023
Kind
B2
Abstract

A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

Claims (37)

1. A semiconductor package, comprising:

a first substrate;

a first layer structure;

a second layer structure; and

a first antenna layer formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure;

wherein the first layer structure is formed between the first substrate and the second layer structure, and wherein the first layer structure comprises a second substrate and a first package body, the second substrate has a receiving portion including an electronic component, and the first package body fills up the receiving portion, the first package body encapsulating the electronic component.

2. The semiconductor package as claimed in claim 1 , further comprising:

a second antenna layer formed on at least one of the first layer structure and the second layer structure.

3. The semiconductor package as claimed in claim 2 , wherein the second layer structure has a layer lower surface, and wherein the second antenna layer has an antenna lower surface substantially flush with the layer lower surface.

4. The semiconductor package as claimed in claim 1 , wherein the first package body has a layer upper surface, and wherein the second layer structure comprises a second package body having a layer lower surface directly contacting the layer upper surface.

5. The semiconductor package as claimed in claim 1 , wherein the second layer structure comprises a second package body, and the first antenna layer is embedded in the second package body.

6. A semiconductor package, comprising:

a first substrate;

a first layer structure;

a second layer structure; and

a first antenna layer formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure;

wherein the second layer structure comprises a molding compound, and wherein the first layer structure comprises a second substrate and a first package body, the second substrate has a receiving portion, and the first package body fills up the receiving portion.

7. The semiconductor package as claimed in claim 6 , further comprising:

a second antenna layer formed on at least one of the first layer structure and the second layer structure.

8. The semiconductor package as claimed in claim 7 , wherein the second layer structure has a layer lower surface, and wherein the second antenna layer has an antenna lower surface substantially flush with the layer lower surface.

9. The semiconductor package as claimed in claim 6 , wherein the first package body has a layer upper surface, and wherein the second layer structure comprises a second package body having a layer lower surface directly contacting the layer upper surface.

10. The semiconductor package as claimed in claim 6 , wherein the second layer structure comprises a second package body, and the first antenna layer is embedded in the second package body.

11. A semiconductor package, comprising:

a first substrate;

a first layer structure comprising a first package body;

a second layer structure comprising a second package body; and

a first antenna layer formed on the second layer structure, wherein the first antenna layer is embedded in the second package body;

wherein the first package body has a layer upper surface, the second package body has a layer lower surface directly contacting the layer upper surface, the first layer structure comprises a second substrate, the second substrate has a receiving portion, and the first package body fills up the receiving portion.

12. The semiconductor package as claimed in claim 11 , further comprising:

a second antenna layer formed on at least one of the first layer structure and the second layer structure.

13. The semiconductor package as claimed in claim 12 , wherein the second layer structure has a layer lower surface, and wherein the second antenna layer has an antenna lower surface substantially flush with the layer lower surface.

14. The semiconductor package as claimed in claim 11 , wherein the first package body has the same material as the second package body.

15. The semiconductor package as claimed in claim 11 , wherein the first antenna layer has an upper surface flush with a layer upper surface of the second layer structure.

16. The semiconductor package as claimed in claim 6 , wherein the receiving portion includes an electronic component, and the first package body encapsulates the electronic component.

17. The semiconductor package as claimed in claim 11 , wherein the receiving portion includes an electronic component, and the first package body encapsulates the electronic component.

18. The semiconductor package as claimed in claim 1 , wherein the first antenna layer is formed on the second layer structure, and wherein the upper surface is flush with the layer upper surface of the second layer structure.

19. The semiconductor package as claimed in claim 6 , wherein the first antenna layer is formed on the second layer structure, and wherein the upper surface is flush with the layer upper surface of the second layer structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2023
From: HSU, WEN-SUNG; CHENG, TAO; CHEN, NAN-CHENG; CHOU, CHE-YA; WU, WEN-CHOU; LU, YEN-JU; HUNG, CHIH-MING; HSU, WEI-HSIU
To: MEDIATEK INC.
Reel/Frame 065062/0884 →
Continuity (7)
Continuation 16994764 · Aug 17, 2020
Continuation 16163614 · Oct 18, 2018
Continuation In Part 15672440 · Aug 9, 2017
Continuation 15162760 · May 24, 2016
Provisional Application 62587624 · Nov 17, 2017
Provisional Application 62221262 · Sep 21, 2015
Related Publication 20220352084A1 · Nov 3, 2022