Hybrid organic and non-organic interposer with embedded component in molding structure and methods for forming the same
Devices and methods of manufacture for a hybrid interposer including a molding structure within a semiconductor device. A semiconductor device may include a semiconductor die, a package substrate, and a hybrid interposer positioned between the semiconductor die and the package substrate. The hybrid interposer may include a molding material layer, and an integrated device positioned within the molding interposer layer. The hybrid interposer may further include an organic material layer, and a non-organic material layer. The molding material layer may include an epoxy molding compound (EMC). The organic material layer may include a dielectric polymer material. The non-organic material layer may include a silicon-based dielectric material.
1 . A method of forming a semiconductor structure, comprising:
forming a package substrate comprising a glass epoxy plate, a board-side surface laminar circuit (SLC) disposed on a board side of the glass epoxy plate, a chip-side SLC disposed on an opposing chip side of the glass epoxy plate, and through-core via structures that extend through the glass epoxy plate to electrically connect the board-side SLC and the chip-side SLC; and
forming a hybrid interposer over a first side of the package substrate by:
depositing an organic material layer;
depositing a non-organic material layer;
forming an integrated passive device positioned above the package substrate;
forming through-substrate via (TSV) structures beside the integrated passive device; and
forming a molding material layer embedding the TSV structures and the integrated passive device,
wherein the molding material layer has a higher Young's modulus than a Young's modulus of the organic material layer;
wherein:
the integrated passive device comprises a resistor, a capacitor, an inductor, a microstrip line, or an impedance matching element and is electrically connected to the package substrate through via device bumps embedded in the molding material layer; and
the via device bumps, the TSV structures, and portions of the integrated passive device are formed by:
depositing a metallic seed layer;
depositing a photoresist layer on the metallic seed layer;
patterning the photoresist layer to expose portions of the seed layer;
depositing a metallic fill material onto the exposed portions of the photoresist layer;
removing the photoresist layer; and
etching portions of the metallic seed layer exposed by the removal of the photoresist layer.
2 . The method of claim 1 , wherein the molding material layer is deposited on the non-organic material layer or the organic material layer.
3 . The method of claim 2 , wherein the organic material layer is deposited on the molding material layer.
4 . The method of claim 1 , wherein the organic material layer is deposited on the non-organic material layer.
5 . The method of claim 1 , wherein the non-organic material layer is deposited on the molding material layer.
6 . The method of claim 5 , wherein the organic material layer is deposited on the non-organic material layer.
7 . The method of claim 1 , wherein the integrated passive device is electrically connected to the package substrate through the TSV structures, and wherein the TSV structures are integrated vias positioned besides the integrated passive device and extend through a depth of the molding material layer.
8 . A method of forming a semiconductor structure, comprising:
forming a hybrid interposer by:
forming a non-organic structure comprising wiring interconnects and through-substrate via (TSV) structures embedded in a non-organic material layer;
forming an organic structure on the non-organic structure, the organic structure comprising wiring interconnects and TSV structures embedded in an organic material layer; and
forming a molding structure on the organic structure, the molding structure comprising an integrated passive device and TSV structures embedded in a molding material layer;
bonding a semiconductor die to a first side of the hybrid interposer; and
bonding a package substrate to a second side of the hybrid interposer, the package substrate comprising a glass epoxy plate, a board-side surface laminar circuit (SLC) disposed on a board side of the glass epoxy plate, a chip-side SLC disposed on an opposing chip side of the glass epoxy plate, and through-core via structures that extend through the glass epoxy plate to electrically connect the board-side SLC and the chip-side SLC,
wherein a Young's modulus of the molding structure is greater than a Young's modulus of the organic structure;
wherein:
the integrated passive device comprises a resistor, a capacitor, an inductor, a microstrip line, or an impedance matching element and is electrically connected to the package substrate through via device bumps embedded in the molding material layer; and
the via device bumps, the TSV structures, and portions of the integrated passive device are formed by:
depositing a metallic seed layer;
depositing a photoresist layer on the metallic seed layer;
patterning the photoresist layer to expose portions of the seed layer;
depositing a metallic fill material onto the exposed portions of the photoresist layer;
removing the photoresist layer; and
etching portions of the metallic seed layer exposed by the removal of the photoresist layer.
9 . The method of claim 8 , wherein the organic structure is disposed between the molding structure and the non-organic structure.
10 . The method of claim 9 , wherein the non-organic structure is disposed between the organic structure and the package substrate.
11 . The method of claim 9 , wherein the molding material layer is disposed between the organic structure and the semiconductor die.
12 . The method of claim 8 , wherein a coefficient of thermal expansion of the molding material layer is lower than a coefficient of thermal expansion of the organic material layer.
13 . The method of claim 12 , wherein the integrated passive device comprises a resistor, a capacitor, an inductor, a microstrip line, or an impedance matching element.
14 . The method of claim 8 , wherein:
the non-organic material layer comprises a silicon-based material; and
the organic material layer comprises an organic polymer material.
15 . A method of forming a semiconductor structure, comprising:
forming a hybrid interposer by:
forming an organic structure comprising wiring interconnects and through-substrate via (TSV) structures embedded in an organic material layer;
forming a non-organic structure on the organic structure, the non-organic structure comprising wiring interconnects and TSV structures embedded in a non-organic material layer; and
forming a molding structure on the non-organic structure, the molding structure comprising an integrated passive device and TSV structures embedded in a molding material layer;
bonding a semiconductor die to a first side of the hybrid interposer; and
bonding a package substrate to a second side of the hybrid interposer, the package substrate comprising a glass epoxy plate, a board-side surface laminar circuit (SLC) disposed on a board side of the glass epoxy plate, a chip-side SLC disposed on an opposing chip side of the glass epoxy plate, and through-core via structures that extend through the glass epoxy plate to electrically connect the board-side SLC and the chip-side SLC,
wherein a coefficient of thermal expansion of the molding material layer is lower than a coefficient of thermal expansion of the organic material layer, and
wherein a Young's modulus of the molding structure is greater than a Young's modulus of the organic structure;
wherein:
the integrated passive device comprises a resistor, a capacitor, an inductor, a microstrip line, or an impedance matching element and is electrically connected to the package substrate through via device bumps embedded in the molding material layer; and
the via device bumps, the TSV structures, and portions of the integrated passive device are formed by:
depositing a metallic seed layer;
depositing a photoresist layer on the metallic seed layer;
patterning the photoresist layer to expose portions of the seed layer;
depositing a metallic fill material onto the exposed portions of the photoresist layer;
removing the photoresist layer; and
etching portions of the metallic seed layer exposed by the removal of the photoresist layer.
16 . The method of claim 15 , wherein the organic structure is disposed between the non-organic structure and the semiconductor die.
17 . The method of claim 15 , wherein the molding structure is disposed between the non-organic structure and the package substrate.
18 . The method of claim 15 , wherein:
the integrated passive device comprises a resistor, a capacitor, an inductor, a microstrip line, or an impedance matching element;
the non-organic material layer comprises a silicon-based material;
the organic material layer comprises an organic polymer material; and
a coefficient of thermal expansion of the molding material layer is lower than a coefficient of thermal expansion of the organic material layer.