Selective liner on backside via and method thereof
A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.
1. A semiconductor structure, comprising:
a source/drain (S/D) feature;
one or more channel semiconductor layers connected to the S/D feature;
a gate structure engaging the one or more channel semiconductor layers;
a first silicide feature at a frontside of the S/D feature;
a second silicide feature at a backside of the S/D feature; and
a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.
2. The semiconductor structure of claim 1 , wherein a height of the first gap is in a range of about 0.2 nm to about 5 nm.
3. The semiconductor structure of claim 2 , wherein the dielectric liner layer includes La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, or ZrSi.
4. The semiconductor structure of claim 3 , wherein the dielectric liner layer has a thickness of about 1 nm to about 5 nm.
5. The semiconductor structure of claim 1 , further comprising a via structure in contact with the second silicide feature, wherein a portion of the via structure is disposed in the first gap.
6. The semiconductor structure of claim 5 , further comprising a metal track in contact with the via structure.
7. The semiconductor structure of claim 1 , further comprising a first dielectric layer at the backside of the S/D feature and in contact with the second silicide feature, wherein a portion of the first dielectric layer is disposed in the first gap.
8. The semiconductor structure of claim 7 , wherein the dielectric liner layer and the first dielectric layer comprise different materials.
9. A semiconductor structure, comprising:
two source/drain (S/D) features;
one or more channel semiconductor layers connecting the two S/D features;
a gate structure engaging the one or more channel semiconductor layers, wherein the two S/D features, the one or more channel semiconductor layer, and the gate structure are at a frontside of the semiconductor structure;
a metal track at a backside of the semiconductor structure;
a first dielectric layer between the metal track and the one or more channel semiconductor layers;
a dielectric liner layer on surfaces of the first dielectric layer and spaced away from a first one of the two S/D features by a first gap; and
a via structure connecting the metal track to the first one of the two S/D features, wherein a portion of the via structure is disposed in the first gap.
10. The semiconductor structure of claim 9 , wherein the dielectric liner layer is spaced away from a second one of the two S/D features by a second gap.
11. The semiconductor structure of claim 10 , wherein a height of the first gap is in a range of about 0.2 nm to about 5 nm, and a height of the second gap is in a range of about 0.2 nm to about 5 nm.
12. The semiconductor structure of claim 10 , further comprising:
a second dielectric layer, wherein a portion of the second dielectric layer is between the metal track and the second one of the two S/D features and fills the second gap.
13. The semiconductor structure of claim 12 , wherein the second dielectric layer and the dielectric liner layer comprise different materials.
14. The semiconductor structure of claim 9 , further comprising a silicide feature between the via structure and the first one of the two S/D features.
15. The semiconductor structure of claim 9 , further comprising a second dielectric layer below the dielectric liner layer and between the first dielectric layer and the metal track.
16. The semiconductor structure of claim 15 , wherein the second dielectric layer and the first dielectric layer comprise different materials.
17. A semiconductor structure, comprising:
a source/drain (S/D) feature;
one or more channel semiconductor layers connected to the S/D feature;
a gate structure engaging the one or more channel semiconductor layers;
an interconnect structure over the gate structure and over a frontside of the S/D feature;
a first dielectric layer below the gate structure;
a silicide feature on a backside of the S/D feature;
a dielectric liner layer on surfaces of the first dielectric layer and spaced away from the silicide feature by a first gap; and
a via structure disposed on the silicide feature, wherein a portion of the via structure is disposed in the first gap.
18. The semiconductor structure of claim 17 , further comprising a metal track in contact with the via structure, wherein the via structure is between the S/D feature and the metal track.
19. The semiconductor structure of claim 18 , further comprising a second dielectric layer, wherein a portion of the second dielectric layer is between the dielectric liner layer and the metal track, wherein the second dielectric layer and the first dielectric layer comprise different materials.
20. The semiconductor structure of claim 19 , wherein the second dielectric layer and the dielectric liner layer comprise different materials.