Displaying base plate and displaying device
View Patent ↗A displaying base plate and a displaying device, the displaying base plate includes a first sub-pixel unit and a second sub-pixel unit that are arranged adjacently, a substrate, and a first metal layer, a first insulating layer and a second metal layer that are arranged in stack on one side of the substrate. The first metal layer includes a first electrode block connected to a constant potential. The second metal layer includes signal lines and connecting lines; the signal lines include a first signal line and a second signal line; the connecting lines include a first connecting line and a second connecting line; the first signal line is connected to a driving circuit of the first sub-pixel unit, the second signal line is connected to a driving circuit of the second sub-pixel unit.
1 . A displaying base plate, wherein the displaying base plate comprises a plurality of sub-pixel units, the plurality of sub-pixel units include a first sub-pixel unit and a second sub-pixel unit that are arranged adjacently, and the displaying base plate comprises a substrate, and a first metal layer, a first insulating layer and a second metal layer that are arranged in stack on one side of the substrate;
wherein, the first metal layer comprises a first electrode block, and the first electrode block is connected to a constant potential;
the second metal layer comprises signal lines and connecting lines; the signal lines include a first signal line and a second signal line; the connecting lines include a first connecting line and a second connecting line; the first signal line is connected to a driving circuit of the first sub-pixel unit, the second signal line is connected to a driving circuit of the second sub-pixel unit, the first connecting line is located inside the first sub-pixel unit, and the second connecting line is located inside the second sub-pixel unit; and
a shielding signal line is provided between the first signal line and the second connecting line, and the shielding signal line is connected to the first electrode block.
2 . The displaying base plate according to claim 1 , wherein the shielding signal line and the second metal layer are arranged in a same layer, and the shielding signal line and the first electrode block are connected by a via hole provided in the first insulating layer.
3 . The displaying base plate according to claim 1 , wherein the shielding signal line and the first metal layer are arranged in a same layer.
4 . The displaying base plate according to claim 1 , wherein an orthographic projection of the shielding signal line on the substrate does not overlaps with an orthographic projection of the signal lines on the substrate.
5 . The displaying base plate according to claim 1 , wherein a direction of extension of the shielding signal line and a direction of extension of the connecting lines are parallel or intersected.
6 . The displaying base plate according to claim 1 , wherein an orthographic projection of the shielding signal line on the substrate is a straight line or a curve line.
7 . The displaying base plate according to claim 1 , wherein the plurality of sub-pixel units are arranged in an array, a direction of arrangement of columns of the plurality of sub-pixel units is a first direction, and an orthographic projection in the first direction of an orthographic projection of the second connecting line on the substrate overlaps with an orthographic projection in the first direction of an orthographic projection of the shielding signal line on the substrate.
8 . The displaying base plate according to claim 7 , wherein the orthographic projection in the first direction of the orthographic projection of the second connecting line on the substrate is located within an area of the orthographic projection in the first direction of the orthographic projection of the shielding signal line on the substrate.
9 . The displaying base plate according to claim 7 , wherein in the first direction, a ratio of a length of the overlapping to a length of the orthographic projection in the first direction of the orthographic projection of the second connecting line on the substrate is greater than or equal to 0.5 and less than or equal to 0.8.
10 . The displaying base plate according to claim 1 , wherein the plurality of sub-pixel units are arranged in an array, a direction of arrangement of columns of the plurality of sub-pixel units is a first direction, and a length of the shielding signal line in the first direction is greater than or equal to 4 μm and less than or equal to 8 μm.
11 . The displaying base plate according to claim 1 , wherein the second metal layer further comprises a power signal line, and the power signal line and the first electrode block are connected by a via hole provided in the first insulating layer.
12 . The displaying base plate according to claim 1 , wherein the displaying base plate further comprises an active layer, a second insulating layer, a grid layer and a third insulating layer that are provided in stack between the substrate and the first metal layer, and the first metal layer is provided on one side of the third insulating layer that is away from the substrate;
wherein, the active layer comprises a first channel region, a second channel region and a first resistor region that connects the first channel region and the second channel region, the grid layer comprises a first grid corresponding to the first channel region and a second grid corresponding to the second channel region, and the first grid is connected to the second grid; and
the first metal layer further comprises a second electrode block, an orthographic projection of the second electrode block on the substrate overlaps with an orthographic projection of the first resistor region on the substrate, and the second electrode block is connected to the shielding signal line.
13 . The displaying base plate according to claim 12 , wherein the orthographic projection of the second electrode block on the substrate covers the orthographic projection of the first resistor region on the substrate.
14 . The displaying base plate according to claim 12 , wherein the active layer further comprises a second resistor region provided on one side of the second channel region that is away from the first resistor region, and the second resistor region is connected to the second channel region; and
the second resistor region and the second connecting line are connected by via holes provided in the first insulating layer, the third insulating layer and the second insulating layer.
15 . The displaying base plate according to claim 14 , wherein the active layer further comprises a third channel region, a third resistor region connecting the third channel region and the first channel region, and a fourth resistor region provided on one side of the third channel region that is away from the third resistor region, and the fourth resistor region is connected to the third channel region;
the grid layer further comprises a third grid corresponding to the third channel region, and the third grid and the second connecting line are connected by via holes provided in the first insulating layer and the third insulating layer; and
the second signal line and the fourth resistor region are connected by via holes provided in the first insulating layer, the third insulating layer and the second insulating layer.
16 . The displaying base plate according to claim 15 , wherein an orthographic projection of the third grid on the substrate overlaps with an orthographic projection of the first electrode block on the substrate.
17 . A displaying device, wherein the displaying device comprises the displaying base plate according to claim 1 .
18 . The displaying base plate according to claim 8 , wherein in the first direction, a ratio of a length of the overlapping to a length of the orthographic projection in the first direction of the orthographic projection of the second connecting line on the substrate is greater than or equal to 0.5 and less than or equal to 0.8.
19 . The displaying base plate according to claim 13 , wherein the active layer further comprises a second resistor region provided on one side of the second channel region that is away from the first resistor region, and the second resistor region is connected to the second channel region; and
the second resistor region and the second connecting line are connected by via holes provided in the first insulating layer, the third insulating layer and the second insulating layer.