Semiconductor device and design method thereof
It is an object of the present invention to achieve a semiconductor device capable of preventing circuit malfunctions caused by noise without decreasing an integration degree of the circuit by making a space between signal interconnections wider and inserting a shield or a shield layer between the signal interconnections. The semiconductor device has a multilayer interconnection structure wherein three or more interconnection layers are stacked on a silicon semiconductor substrate, and comprises: a first signal line which is formed with a (N−1)-th interconnection layer and comprises a latch circuit; a second signal line which is formed with a (N+1)-th interconnection layer and is arranged so as to cross the first signal line or partially overlap thereover; and a power supply interconnection serving as a shield interconnection which is formed with an N-th interconnection layer in a portion directly beneath the first signal line and the second signal line.
1. In a semiconductor device wherein a plurality of interconnection layers including a (N−1)-th (N is an integer equal to two or more) interconnection layer, and an N-th interconnection layer are stacked on a substrate from a lower layer to an upper layer in order, and insulating layers are provided between the substrate and the lowest interconnection layer, and between respective interconnection layers, respectively, the semiconductor device, comprising:
at least one functional block of a first type and at least one functional block of a second type, different from said first type, collectively arranged with said (N−1)-th interconnection layer; and
a shield layer formed with said N-th interconnection layer and over said at least one functional block of the first type but not said at least one functional block of the second type.
2. A semiconductor device, wherein semiconductor elements are formed on a substrate, the semiconductor device comprising:
at least one functional block including a plurality of logic cells, and
a shield layer arranged to cover at least one of the plurality of logic cells but not the other one of the plurality of logic cells.
3. The semiconductor device according to claim 2 , wherein said shield layer is also used as a power supply interconnection.
4. The semiconductor device according to claim 3 , wherein said power supply interconnection is provided with a fixed voltage.
5. The semiconductor device according to claim 2 , wherein said at least one functional block is dynamically controlled.
6. The semiconductor device according to claim 2 , wherein a power potential of said functional block is capable of being varied by a level shifter.
7. The semiconductor device according to claim 2 , wherein a substrate voltage potential of said functional block is capable of being varied by a level shifter.
8. The semiconductor device according to claim 2 , wherein said substrate is a silicon semiconductor substrate or an SOI substrate.
9. The semiconductor device according to claim 2 , wherein said at least one functional block is a latch circuit.