Thin film transistor comprising crystalline IZTO oxide semiconductor, and method for producing same
View Patent ↗A crystalline IZTO oxide semiconductor and a thin film transistor having the same are provided. The thin film transistor includes a gate electrode, a crystalline In—Zn—Sn oxide (IZTO) channel layer overlapping the upper or lower portions of the gate electrode and having hexagonal crystal grains, and a gate insulating layer disposed between the gate electrode and the IZTO channel layer, and source and drain electrodes respectively connected to both ends of the IZTO channel layer.
1 . A thin film transistor comprising:
a gate electrode;
a crystalline In—Zn—Sn oxide (IZTO) channel layer overlapping the upper or lower portions of the gate electrode and having hexagonal crystal grains;
a gate insulating layer disposed between the gate electrode and the IZTO channel layer; and
source and drain electrodes respectively connected to both ends of the IZTO channel layer,
wherein the hexagonal crystal grains are crystal grains having a (ZnO) k In 2 O 3 (k is an integer of 3 to 11) phase and the IZTO channel layer further has (x)ZnIn 2 O 4 -(1-x)Zn 2 SnO 4 (0<x<0.45), as a sub-solid phase.
2 . The thin film transistor of claim 1 , wherein the k is 5 in the (ZnO) k In 2 O 3 phase.
3 . The thin film transistor of claim 1 , wherein SnO 2 is mixed in the (ZnO) k In 2 O 3 (k is an integer of 3 to 11) phase to exist in the form of a solid solution.
4 . A thin film transistor, comprising:
a gate electrode;
a crystalline In—Zn—Sn oxide (IZTO) channel layer overlapping the upper or lower portions of the gate electrode and having hexagonal crystal grains;
a gate insulating layer disposed between the gate electrode and the IZTO channel layer; and
source and drain electrodes respectively connected to both ends of the IZTO channel layer,
wherein the XRD graph for the IZTO channel layer shows a diffraction peak corresponding to (0021) plane.
5 . The thin film transistor of claim 4 , wherein a full width at half maximum (FWHM) of the diffraction peak is about 0.3 to 0.5 radians.
6 . The thin film transistor of claim 1 , wherein the IZTO channel layer has 21 to 25 at % of indium (In), 54 to 57 at % of zinc (Zn), and 19 to 22 at % of tin (Sn) when the sum of the number of atoms of indium, zinc, and tin is 100%.
7 . The thin film transistor of claim 6 , wherein the IZTO channel layer has 22.5 to 23.5 at % of In, 54.7 to 55.5 at % of Zn, and 20.5 to 21.3 at % of Sn when the sum of the number of atoms of indium, zinc, and tin is 100%.
8 . A preparation method for a crystalline IZTO comprising:
forming an amorphous In—Zn—Sn oxide (IZTO) layer on a substrate;
forming a transition metal layer containing a transition metal having a large oxidation tendency compared to In, Zn, and Sn under the amorphous IZTO layer before forming the amorphous IZTO layer or on the amorphous IZTO layer after forming the amorphous IZTO layer; and
changing the amorphous IZTO layer into a crystalline IZTO layer having hexagonal crystal grains by performing a crystallization heat treatment on the substrate on which the amorphous IZTO layer and the transition metal layer are formed,
wherein the hexagonal crystal grains are crystal grains having a (ZnO) k In 2 O 3 (k is an integer of 3 to 11) phase and the IZTO channel layer further has (x)ZnIn 2 O 4 -(1-x)Zn 2 SnO 4 (0<x<0.45), as a sub-solid phase.
9 . The preparation method of claim 8 , wherein the amorphous IZTO layer has 21 to 25 at % of indium (In), 54 to 57 at % of zinc (Zn), and 19 to 22 at % of tin (Sn) when the sum of the number of atoms of indium, zinc, and tin is 100%.
10 . The preparation method of claim 9 , wherein the amorphous IZTO layer has 22.5 to 23.5 at % of In, 54.7 to 55.5 at % of Zn, and 20.5 to 21.3 at % of Sn when the sum of the number of atoms of indium, zinc, and tin is 100%.
11 . The preparation method of claim 8 , wherein the heat treatment temperature is 270° C. to 350° C.
12 . The preparation method of claim 8 , wherein the transition metal layer is a Ta layer.
13 . The preparation method of claim 8 , wherein the hexagonal crystal grains are crystal grains having a (ZnO) k In 2 O 3 (k is 5) phase.
14 . A method for preparation a thin film transistor including a gate electrode on a substrate; a channel layer overlapping the upper or lower portions of the gate electrode; a gate insulating layer disposed between the gate electrode and the channel layer; and source and drain electrodes respectively connected to both ends of the channel layer, comprising:
forming an amorphous In—Zn—Sn oxide (IZTO) layer;
forming a transition metal layer containing a transition metal having a large oxidation tendency compared to In, Zn, and Sn under the amorphous IZTO layer before forming the amorphous IZTO layer or on the amorphous IZTO layer after forming the amorphous IZTO layer; and
changing the amorphous IZTO layer into a crystalline IZTO layer having hexagonal crystal grains by performing a crystallization heat treatment on the substrate on which the amorphous IZTO layer and the transition metal layer are formed,
wherein the crystalline IZTO layer is the channel layer, and
wherein the hexagonal crystal grains are crystal grains having a (ZnO) k In 2 O 3 (k is an integer of 3 to 11) phase and the IZTO channel layer further has (x)ZnIn 2 O 4 -(1-x)Zn 2 SnO 4 (0<x<0.45), as a sub-solid phase.
15 . The preparation method of claim 14 , wherein the amorphous IZTO layer has 21 to 25 at % of indium (In), 54 to 57 at % of zinc (Zn), and 19 to 22 at % of tin (Sn) when the sum of the number of atoms of indium, zinc, and tin is 100%.
16 . The preparation method of claim 14 , wherein the transition metal layer is a Ta layer.
17 . The preparation method of claim 14 , wherein the hexagonal crystal grains are crystal grains having a (ZnO) k In 2 O 3 (k is 5) phase.