Apparatuses and methods including multilevel command and address signals
View Patent ↗Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.
1. An apparatus, comprising:
an address decoder configured to receive address signals and provide decoded addresses;
a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations; and
a command/address input circuit configured to receive a plurality of multilevel command and address signals and provide output signals representing values of the plurality of multilevel command and address signals to the address decoder and the command decoder, wherein each multilevel command and address signal has a respective voltage corresponding to one of three or more different values, wherein the command/address input circuit comprises:
a multilevel input buffer configured to receive the multilevel command and address signals and provide respective output signals for each of the multilevel command and address signals;
a command and address input decoder circuit configured to receive the output signals from the multilevel input buffer and configured to provide decoded signals representing the voltages of the multilevel command and address signals to the address decoder: and
a signal latch configured to latch the output signals from the multilevel input buffer and provide the latched output signals to the command decoder.
2. The apparatus of claim I wherein each multilevel command and address signal has a voltage corresponding to a 0, 1, or 2.
3. The apparatus of claim I wherein the values of the plurality, of multilevel command and address signals provided to the address decoder are represented by bits and the values of the plurality of multilevel command and address signals provided to the command decoder are represented by output signals having logic levels that correspond to non-binary values.
4. The apparatus of claim 3 wherein the command/address input circuit is configured to provide three bits to the address decoder based on the values of two multilevel command and address signals.
5. The apparatus of claim 3 wherein the command/address input circuit is configured to provide four output signals to the command decoder based on two multilevel command and address signals.
6. A method comprising:
receiving, at an address decoder, address signals
providing with the address decoder. decoded addresses based on the address signals;
receiving, at a command decoder, internal command signals;
providing, with the command decoder, internal control signals for performing memory operations based on the internal command signals;
receiving, at a commandla.ddress input circuit, a plurality of multilevel command and address signals;
providing, with the command/address input circuit, output signals representing values of the plurality of multilevel command and address signals to the address decoder and the command decoder, wherein each multilevel command and address signal has a respective voltage corresponding to one of three or more different values;
receiving, at a multilevel input buffer of the command/address input circuit, the plurality multilevel command and address signals;
providing, with the multilevel input buffer, respective output signals for each of the multilevel command and address signals;
receiving, at a command and address input decoder circuit of the command/address input circuit, the output signals from the multilevel input buffer:
providing, with the command and address input decoder, decoded signals representing the voltages of the multilevel command and address signals to the address decoder;
latching with a signal latch of the command/address input circuit, the output signals from the multilevel input buffer:, and
providing, from the signal latch, the latched output signals to the command decoder.
7. The method of claim 6 , wherein each multilevel command and address signal has a voltage corresponding to a 0, 1, or 2.
8. The method of claim 6 wherein the values of the plurality of multilevel command and address signals provided to the address decoder are represented by bits and the values of the plurality of multilevel command and address signals provided to the command decoder are represented by output signals having logic levels that correspond to non-binary values.
9. The method of claim 6 , further comprising providing, with the command/address input circuit, three bits to the address decoder based on the values of two multilevel command and address signals.
10. The method of claim 6 , further comprising providing, with the commandladdress input circuit, four output signals to the command decoder based on two multilevel command and address signals.
11. An apparatus comprising:
a command/address input circuit configured to receive a plurality of multilevel command and address signals and provide output signals representing values of the plurality of multilevel command and address signals to an address decoder and a command decoder, wherein each multilevel command and address signal has a respective voltage corresponding to one of three or more different values, wherein the command/address input circuit comprises:
a command and address input decoder circuit configured to provide decoded signals representing the voltages of the multilevel command and address signals to an address decoder; and
a signal latch configured to latch the output signals and provide the latched signals to the command decoder.
12. The apparatus of claim 11 , further comprising:
the address decoder configured to receive address signals and provide decoded addresses; and
the command decoder configured to receive internal command signals and provide internal control signals for performing memory operations.
13. The apparatus of claim 11 , wherein the command/address input circuit provides a plurality of output signals for each one of the plurality of multilevel command and address signals.
14. The apparatus of claim 13 , wherein each of the plurality of output signals has a first state and a second state.
15. The apparatus of claim 11 , wherein the command/address input circuit comprises an input buffer configured to receive the plurality of multilevel command and address signals.
16. The apparatus of claim 11 , wherein the command/address input circuit is configured to receive a clock signal.