Apparatuses and methods including multilevel command and address signals
View Patent ↗Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.
1. An apparatus, comprising:
a memory configured to receive a plurality of multilevel command and address signals that represent a command structure including a command operand and memory addresses, the multilevel command and address signals having respective voltages corresponding to a non-binary value, wherein the memory includes:
a means for providing internal command signals representing the command operand based on the multilevel command and address signals, wherein the means for providing internal command signals comprises a latching means that provides bits of the command operand based on two of the multilevel command and address signals;
a means for providing internal address signals representing the memory addresses, the memory addresses including a plurality of bits represented by the internal address signals wherein the means for providing internal address signals comprises a decoding means that provides bits of the memory addresses based on two of the multilevel command and address signals; and
a means for performing memory operations based on the internal command signals on memory locations based on the internal address signals.
2. The apparatus of claim 1 , further comprising
a controller configured to provide the plurality of multilevel command and address signals to the memory; and
a means of coupling the controller and the memory.
3. The apparatus of claim 1 , the memory further comprising a means of decoding the multilevel command and address signals into binary values.
4. The apparatus of claim 1 , the memory further comprising a means of comparing the voltages to a first reference voltage.
5. The apparatus of claim 4 , the memory further comprising a means of comparing the voltages to a second reference voltage.
6. The apparatus of claim 1 , wherein each multilevel command and address signal has a respective voltage corresponding to one of three or more different values.
7. The apparatus of claim 1 , wherein each multilevel command and address signal has a voltage corresponding to a 0, 1, or 2.
8. The apparatus of claim 1 , the memory further comprising a means of latching signals corresponding to the command operand.
9. A method comprising:
receiving, at a memory, a plurality of multilevel command and address signals that represent a command structure including a command operand and memory addresses, the multilevel command and address signals having respective voltages corresponding to a non-binary value;
converting the multilevel command and address signals to binary signals;
latching the binary signals;
providing internal command signals representing the command operand based on the binary signals latched;
decoding the binary signals;
providing internal address signals representing the memory addresses, the memory addresses including a plurality of bits based on the binary signals decoded; and
performing memory operations based on the internal command signals on memory locations based on the internal address signals.
10. The method of claim 9 , further comprising receiving a clock signal at the memory, wherein a portion of the plurality of multilevel command and address signals are received on a rising edge of the clock signal and another portion of the plurality of multilevel command and address signals are received on a falling edge of the clock signal.
11. The method of claim 9 , further comprising receiving a select signal at the memory.
12. The method of claim 9 , further comprising decoding the multilevel command and address signals into binary values.
13. The method of claim 9 , further comprising comparing the voltages to at least one reference voltage.
14. The method of claim 9 , wherein each multilevel command and address signal has a respective voltage corresponding to one of three or more different values.
15. The method of claim 9 , wherein the command structure further comprises a multipurpose output.
16. The method of claim 9 , wherein the memory operations include an activation operation, a precharge operation, a write operation, a read operation, a mask write operation, or a combination thereof.
17. A system comprising:
a plurality of memories, wherein each of the memories is configured to receive a plurality of multilevel command and address signals that represent a command structure including a command operand and memory addresses, the multilevel command and address signals having respective voltages corresponding to a non-binary value, wherein each of the plurality of memories includes:
a means of decoding the multilevel command and address signals into binary values;
a means of latching the binary values;
a means for providing internal command signals representing the command operand based on the binary values latched;
a means of decoding the binary values;
a means for providing internal address signals representing the memory addresses, the memory addresses including a plurality of bits based on the binary values decoded; and
a means for performing memory operations based on the internal command signals on memory locations based on the internal address signals.
18. The system of claim 17 , further comprising:
a controller configured to provide the plurality of multilevel command and address signals to the plurality of memories; and
a means of coupling the controller and the plurality of memories.
19. The system of claim 18 , wherein the controller is further configured to provide a clock signal to the plurality of memories.
20. The system of claim 17 , each of the plurality of memories further comprising a means of decoding the multilevel command and address signals into binary values.