Multigate device structure with engineered cladding and method making the same
The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.
1. A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate;
patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench;
epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region;
forming an isolation feature in the trench;
performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and
forming a cladding layer of the second semiconductor material over the silicon nitride layer.
2. The method of claim 1 , further comprising forming a dielectric layer on the liner before the performing a rapid thermal nitridation process.
3. The method of claim 2 , wherein
the dielectric layer includes silicon oxide;
the first semiconductor material is silicon; and
the second semiconductor material is silicon germanium.
4. The method of claim 2 , further comprising removing the dielectric layer after the performing a rapid thermal nitridation process and before the forming a cladding layer.
5. The method of claim 4 , wherein the removing the dielectric layer includes
performing a chemical oxide removal (COR) process; and
performing a post heating treatment (PHT).
6. The method of claim 5 , wherein
the COR process includes applying NH3 and HF at a first temperature; and
the PHT includes applying an annealing process at a second temperature greater than the first temperature.
7. The method of claim 1 , wherein the forming a cladding layer includes
depositing the cladding layer on the active region such that the cladding layer is separated from the semiconductor stack by the silicon nitride layer; and
performing an anisotropic etching process to the cladding layer.
8. The method of claim 7 , wherein
the depositing the cladding layer on the active region includes depositing the cladding layer with a first portion on the silicon nitride and a second portion on the liner;
the first portion of the cladding layer has an amorphous structure; and
the second portion of the cladding layer has a crystalline structure.
9. The method of claim 1 , further comprising:
forming a dummy gate stack on the active region;
forming source/drain (S/D) features on the active region and connecting to the first semiconductor layers;
removing the dummy gate stacks, resulting in a gate trench in an interlayer dielectric (ILD) layer;
performing an etching process in the gate trench to selectively remove the cladding layer and the second semiconductor layers; and
forming a gate stack in the gate trench, the gate stack wrapping around each of the first semiconductor layers.
10. A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate;
patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench;
forming an isolation feature in the trench;
forming a diffusion blocking layer on sidewalls of the active region; and
forming a cladding layer of the second semiconductor material on the diffusion blocking layer.
11. The method of claim 10 , further comprising:
forming a dummy gate stack on the cladding layer;
forming source/drain (S/D) features on the active region and connecting to the first semiconductor layers;
removing the dummy gate stacks, resulting in a gate trench in an interlayer dielectric (ILD) layer;
performing an etching process in the gate trench to selectively remove the cladding layer and the second semiconductor layers; and
forming a gate stack in the gate trench, the gate stack wrapping around each of the first semiconductor layers.
12. The method of claim 10 , wherein the forming diffusion blocking layer further includes
epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region before the forming an isolation feature in the trench; and
forming a dielectric layer on the liner after the forming an isolation feature in the trench.
13. The method of claim 12 , wherein
the dielectric layer includes silicon oxide;
the first semiconductor material is silicon; and
the second semiconductor material is silicon germanium.
14. The method of claim 13 , wherein the forming diffusion blocking layer further includes performing an in-situ carbon (ISC) process to form a carbon-rich dielectric layer on the dielectric layer, and wherein the forming a cladding layer includes forming the cladding layer of the second semiconductor material on the carbon-rich dielectric layer.
15. The method of claim 14 , wherein the performing an ISC process includes applying a precursor containing
16. The method of claim 13 , wherein the forming a diffusion blocking layer further includes performing a rapid thermal nitridation (RTN) process, thereby converting the liner into a silicon nitride layer.
17. The method of claim 16 , further comprising removing the dielectric layer after the performing a rapid thermal nitridation process and before the forming a cladding layer.
18. The method of claim 17 , wherein the removing the dielectric layer includes
applying NH3 and HF at a first temperature; and
applying a post heating treatment at a second temperature being greater than the first temperature.
19. A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate;
patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench;
epitaxially growing a silicon layer on sidewalls of the trench and sidewalls of the active region, thereby forming a liner;
forming an isolation feature in the trench;
etching to remove exposed portion of the liner; and
epitaxially growing a cladding layer of the second semiconductor material such that the cladding layer is grown selectively on the active region relative to the isolation feature, wherein the cladding layer is in a crystalline structure.
20. The method of claim 19 , wherein the cladding layer is free from surfaces of the isolation feature.