Test element group and test device including the same
A test device includes semiconductor substrate, gate lines disposed on an upper surface of the semiconductor substrate and extending in a first direction parallel to the upper surface, a test element group including test transistors defined by the gate lines and by active regions extending in a second direction perpendicular to the first direction and intersecting the gate lines, and metal wirings disposed on the semiconductor substrate and electrically connected to the active regions and/or the gate lines, and a test circuit electrically connected to the metal wirings and configured to measure resistance of the test transistors. The gate lines include first gate lines and second gate lines disposed alternately, with the spacing between first gate lines and second gate lines alternating between a first distance and a second distance greater than the first distance.
1. A test device of a semiconductor device, comprising:
a semiconductor substrate;
a plurality of gate lines disposed on an upper surface of the semiconductor substrate and extending in a first direction parallel to the upper surface;
a test element group including a plurality of test transistors defined by the plurality of gate lines and by a plurality of active regions intersecting the plurality of gate lines and extending in a second direction parallel to the upper surface and perpendicular to the first direction, and further including a plurality of metal wirings disposed on the semiconductor substrate and electrically connected to the plurality of active regions and/or the plurality of gate lines; and
a test circuit electrically connected to a portion of the plurality of metal wirings and configured to measure resistance of the plurality of test transistors,
wherein the plurality of gate lines includes a plurality of first gate lines and a plurality of second gate lines, wherein each of the plurality of first gate lines is disposed alternately with each of the plurality of second gate lines, wherein each of the plurality of first gate lines is spaced apart by a first distance from one of the plurality of second gate lines in the second direction on one side, and is spaced apart by a second distance greater than the first distance from another second gate line of the plurality of second gate lines in the second direction on the other side.
2. The test device of claim 1 , wherein the test element group includes a first contact configured to connect one of the plurality of active regions to each of the plurality of metal wirings that are electrically connected to the test circuit.
3. The test device of claim 1 , wherein the test element group includes a first contact configured to connect one of the plurality of active regions to at least one of the metal wirings electrically connected to the test circuit, and includes a second contact configured to connect one of the plurality of gate lines to another one of the metal wirings electrically connected to the test circuit.
4. The test device of claim 1 , wherein the test circuit measures a resistance of the plurality of test transistors before a constituent structure of the semiconductor device is formed on the plurality of metal wirings.
5. The test device of claim 4 , wherein the test circuit determines that there is a defect in at least one of the plurality of test transistors when resistance of the plurality of test transistors is greater than about 30 kΩ.
6. The test device of claim 4 , wherein the test circuit detects a defective transistor based on a connection structure of the plurality of test transistors according to a magnitude of the measured resistance.
7. The test device of claim 4 , wherein the plurality of test transistors each have a same structure.
8. The test device of claim 1 , wherein each of the plurality of test transistors are connected to each other in series by the plurality of metal wirings.
9. The test device of claim 1 , wherein a first contact extending in a third direction perpendicular to the first and second directions and penetrating into a portion of each of the plurality of active regions is disposed on the plurality of active regions, and
wherein, a length in the third direction of the first contact disposed between a pair of the plurality of gate lines spaced apart from each other by a first distance is less than a length in the third direction of the first contact disposed between another pair of the plurality of gate lines spaced apart from each other by a second distance.
10. The test device of claim 1 , wherein a first contact extending in a third direction perpendicular to the first and second directions and equally spaced apart from adjacent gate lines among the plurality of gate lines is disposed in each of the plurality of active regions.
11. A test element group, comprising:
a plurality of gate lines extending in a first direction parallel to an upper surface of a semiconductor substrate, and including a plurality of first gate lines and a plurality of second gate lines, wherein each of the plurality of first gate lines is disposed alternately with each of the plurality of second gate lines;
a plurality of test transistors defined by the plurality of gate lines;
a plurality of active regions intersecting the plurality of gate lines and spaced apart from each other in the first direction; and
a plurality of metal wirings disposed on the semiconductor substrate and electrically connected to the plurality of active regions and/or the plurality of gate lines,
wherein each of the plurality of first gate lines is spaced apart by a first distance from one of the plurality of second gate lines on one side, wherein each of the plurality of first gate lines is spaced apart by a second distance greater than the first distance from another one of the plurality of second gate lines on the other side in the second direction, and wherein the second direction is parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction, and a sum of the first distance and the second distance has a predetermined value regardless of a location of the first gale line.
12. The test element group of claim 11 , wherein a difference between the first distance and the second distance is between 2 nm and 8 nm.
13. The test element group of claim 11 , wherein each of the plurality of test transistors includes at least one fin structure providing the plurality of active regions.
14. The test element group of claim 11 , wherein each of the plurality of test transistors includes at least one nanosheet providing the plurality of active regions.
15. A test element group, comprising:
a plurality of gate lines extending in a first direction parallel to an upper surface of a semiconductor substrate and including a plurality of first gate lines and a plurality of second gate lines, wherein each of the plurality of first gate lines is disposed alternately with each of the plurality of second gate lines;
a plurality of test transistors defined by the plurality of gate lines, and by a plurality of active regions intersecting the plurality of gate lines, the plurality of active regions spaced apart from each other in the first direction;
a plurality of metal wirings disposed on the semiconductor substrate and electrically connected to the plurality of active regions and/or the plurality of gate lines; and
a plurality of contacts connecting at least one of the plurality of metal wirings to at least one of the plurality of active regions,
wherein each of the plurality of first gate lines is spaced apart by a first distance from one of the plurality of second gate lines on one side in a second direction, and is spaced apart by a second distance greater than the first distance from another one of the plurality of second gate lines on the other side in the second direction, wherein the second direction is parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction, and wherein a distance between adjacent contacts among the plurality of contacts is different from the first distance and the second distance.
16. The test element group of claim 15 , wherein the distance between adjacent contacts is constant for all adjacent contacts among the plurality of contacts.
17. The test element group of claim 15 , wherein the plurality of gate lines is formed based on the configuration of a plurality of position control patterns formed on one side of the semiconductor substrate in the first direction.
18. The test element group of claim 17 , wherein a length of each of the plurality of position control patterns in the second direction determines the first distance.
19. The test element group of claim 17 , wherein a distance between each of the plurality of position control patterns determines the second distance.
20. The test element group of claim 17 , wherein the length of each of the plurality of position control patterns in the second direction is the same, and wherein spacing distances between each of the plurality of position control patterns are the same.