IP Library › Granted Patent US 12,422,617
Granted Patent B2
US 12,422,617 · App. 17/807,257 · Granted Sep 23, 2025

Photonic integrated circuit including passive optical guard

Inventors: Zhuojie Wu (Port Chester, NY); Yusheng Bian (Ballston Lake, NY); Andreas D. Stricker (Essex Junction, VT)
Assignee: GlobalFoundries U.S. Inc.
G02B6/122G02B6/13G02B2006/12126
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Quick Facts
Patent No.
US 12,422,617
App. No.
17/807,257
Granted
Sep 23, 2025
Kind
B2
Abstract

The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. A passive optical guard is composed of a light absorbing material and is in proximity to the photonic component. The passive optical guard includes at least a portion in an active semiconductor layer of the semiconductor substrate and may be entirely below a first metal layer. The passive optical guard may include at least one of: a germanium body positioned at least partially in a silicon element in the active semiconductor layer, a silicon body having a high dopant concentration in the active semiconductor layer, and a polysilicon body having a high dopant concentration over the silicon body.

Claims (31)

1. A photonic integrated circuit (PIC) structure, comprising:

a photonic component, wherein at least a portion of the photonic component is positioned in an active semiconductor layer of a semiconductor substrate;

a passive optical guard composed of a light absorbing material and in proximity to the photonic component, wherein the passive optical guard includes at least a portion positioned in the active semiconductor layer of the semiconductor substrate, and wherein the passive optical guard is entirely below a first metal layer and above a base semiconductor layer of the PIC structure; and

an insulator layer separating the photonic component and the passive optical guard.

2. The PIC structure of claim 1 , wherein the passive optical guard substantially surrounds the photonic component, wherein the photonic component is one of a plurality of photonic components in the PIC structure.

3. The PIC structure of claim 2 , further comprising an optical waveguide extending through a gap in the passive optical guard, the optical waveguide in optical communication with the photonic component.

4. The PIC structure of claim 1 , wherein the passive optical guard includes a pair of elongated elements extending along opposing sides of the photonic component.

5. The PIC structure of claim 1 , wherein the passive optical guard includes a germanium body positioned at least partially in a silicon element.

6. The PIC structure of claim 5 , wherein the silicon element is positioned in the active semiconductor layer.

7. The PIC structure of claim 1 , wherein the passive optical guard includes a silicon body in the active semiconductor layer and having a high dopant concentration.

8. The PIC structure of claim 7 , wherein the optical guard further includes a polysilicon body having a high dopant concentration over the silicon body.

9. The PIC structure of claim 1 , wherein the passive optical guard includes at least one of: a germanium body positioned at least partially in a silicon element in the active semiconductor layer, a silicon body in the active semiconductor layer having a high dopant concentration, and a polysilicon body having a high dopant concentration over the silicon body.

10. The PIC structure of claim 1 , wherein the photonic component includes an optical absorber including a spiral waveguide body and a linear input waveguide coupled to the spiral waveguide body, and wherein the passive optical guard surrounds the spiral waveguide body and the linear input waveguide.

11. The PIC structure of claim 1 , wherein the passive optical guard includes at least a pair of spaced optical guard elements, each including the light absorbing material.

12. The PIC structure of claim 1 , wherein the passive optical guard has an L-shape having a first leg adjacent a portion of the photonic component, and a second leg adjacent a waveguide in optical communication with the photonic component.

13. The PIC structure of claim 1 , wherein the photonic component includes at least one of: a photodetector, an avalanche photodiode (APD), an optical waveguide, an optical input/output coupler, and an optical absorber.

14. A photonic integrated circuit (PIC) structure, comprising:

a photonic component, wherein at least a portion of the photonic component is positioned in an active layer of a semiconductor substrate;

a passive optical guard composed of a light absorbing material and in proximity to the photonic component, the passive optical guard entirely below a first metal layer and above a base semiconductor layer of the PIC structure and including at least a portion in the active semiconductor layer of the semiconductor substrate; and

an insulator layer separating the photonic component and the passive optical guard, wherein the insulator layer includes an oxide,

wherein the passive optical guard includes at least one of: a germanium body positioned at least partially in a silicon element in the active semiconductor layer, a silicon body having a high dopant concentration in the active semiconductor layer, and a polysilicon body having a high dopant concentration over the silicon body.

15. A photonic integrated circuit (PIC) structure, comprising:

a silicon-on-insulator (SOI) substrate including an active semiconductor layer, a base semiconductor layer, and an insulating layer separating the active semiconductor layer from the base semiconductor layer;

a photonic component positioned at least partially in the active semiconductor layer of the SOI substrate;

a passive optical guard composed of a light absorbing material and in proximity to the photonic component, wherein the passive optical guard includes at least a portion positioned in the active semiconductor layer of the SOI substrate, and wherein the passive optical guard is entirely below a first metal layer and above a base semiconductor layer of the PIC structure; and

an insulator layer separating the photonic component and the passive optical guard.

16. The PIC structure of claim 15 , wherein the passive optical guard includes a germanium body positioned at least partially in a silicon element, and wherein the silicon element is positioned in the active semiconductor layer of the SOI substrate.

17. The PIC structure of claim 15 , wherein the passive optical guard includes a silicon body in the active semiconductor layer of the SOI substrate and having a high dopant concentration.

18. The PIC structure of claim 17 , wherein the optical guard further includes a polysilicon body having a high dopant concentration over the silicon body.

19. The PIC structure of claim 1 , wherein the insulator layer separating the photonic component and the passive optical guard includes an oxide.

20. The PIC structure of claim 15 , wherein the insulator layer separating the photonic component and the passive optical guard includes an oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2022
From: WU, ZHUOJIE; BIAN, YUSHENG; STRICKER, ANDREAS D.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 060236/0681 →
Continuity (1)
Related Publication 20230408763A1 · Dec 21, 2023
References Cited (40)
US 2557110A · Jaynes · 1951 [cited by applicant]
US 2619538A · Grant · 1952 [cited by applicant]
US 6970611B1 · Van Der Vliet · 2005 [cited by examiner]
US 7116880B1 · Liu et al. · 2006 [cited by applicant]
US 8089285B2 · Hsu et al. · 2012 [cited by applicant]
US 8664047B2 · Lower et al. · 2014 [cited by applicant]
US 9075251B2 · Dwivedi et al. · 2015 [cited by applicant]
US 11163114B2 · Bian et al. · 2021 [cited by applicant]
US 20030143769A1 · Baek · 2003 [cited by examiner]
US 20100006908A1 · Brady · 2010 [cited by applicant]
US 20130113968A1 · Lenchenkov et al. · 2013 [cited by applicant]
US 20150192735A1 · Ellis-Monaghan · 2015 [cited by applicant]
US 20170168234A1 · Shi · 2017 [cited by applicant]
US 20170322373A1 · Shi et al. · 2017 [cited by applicant]
US 20180267150A1 · Inada · 2018 [cited by applicant]
US 20190025504A1 · Tsujita · 2019 [cited by applicant]
US 20210055477A1 · Bian · 2021 [cited by applicant]
US 20210149136A1 · Nomura · 2021 [cited by applicant]
US 20210167230A1 · Pelletier · 2021 [cited by applicant]
US 20210396929A1 · Bian et al. · 2021 [cited by applicant]
US 20220149098A1 · Wang · 2022 [cited by examiner]
US 20230113261A1 · Augur · 2023 [cited by examiner]
Bian et al., “Light manipulation in a monolithic silicon photonics platform leveraging 3D coupling and decoupling,” Frontiers in Optics, Laser Science, FTu6E.3.pdf, OSA 2020, 3 pages. [cited by applicant]
Bian et al., “3D silicon photonic interconnects and integrated circuits based on phase matching,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2279-84, 6 pages. [cited by applicant]
Lockwood et al., “Optical Properties of Germanium Dots Self-Assembled on Porous TiO2 Templates,” ECS Transactions, 33:147-165, 2011, 20 pages. [cited by applicant]
Shen et al., “Increasing the density of passive photonic-integrated circuits via nanophotonic cloaking,” Nature Communications, 7:13126, Nov. 2016, 9 pages. [cited by applicant]
Yakimov et al., “Electromodulated reflectance study of self-assembled Ge/Si quantum dots.” Nanoscale Research Letters, 6:208, 2011, 5 pages. [cited by applicant]
Aboketaf et al., “Towards fully automated testing and characterization for photonic compact modeling on 300-mm wafer platform,” W6A.1, OFC 2021, OSA 2021, 3 pages. [cited by applicant]
Bian et al., “3D Integrated Laser Attach Technology on 300-mm Monolithic Silicon Photonics Platform,” 978-1-7281-5891-4/20, IEEE 2020, 2 pages. [cited by applicant]
Bian et al., “Towards low-loss monolithic silicon and nitride photonic building blocks in state-of-the-art 300mm CMOS foundry,” FW5D.2, Frontiers in Optics, Laser Science, OSA 2020, 2 pages. [cited by applicant]
Bian et al., “Monolithically integrated silicon nitride platform,” Th1A.46, OFC 2021, OSA 2021, 3 pages. [cited by applicant]
Bian et al., “Hybrid III-V laser integration on a monolithic silicon photonic platform,” M5A.2, OFC 2021, OSA 2021, 3 pages. [cited by applicant]
Chowdhury et al., “High Performance Avalanche Photodiode in a Monolithic Silicon Photonics Technology,” W3D.1, OFC 2022, Optica Publishing Group 2022, 3 pages. [cited by applicant]
Giewont et al., “300-mm Monolithic Silicon Photonics Foundry Technology,” IEEE Journal of Selected Topics in Quantum Electronics, 25:8200611, Sep./Oct. 2019, 12 pages. [cited by applicant]
Peng et al., A CMOS Compatible Monolithic Fiber Attach Solution with Reliable Performance and Self-Alignment, Th3l.4, OFC 2020, OSA 2020, 3 pages. [cited by applicant]
Rakowski et al., “45nm CMOS—Silicon Photonics Monolithic Technology (45CLO) for next-generation, low power and high speed optical interconnects,” T3H.3, OFC 2020, OSA 2020, 3 pages. [cited by applicant]
U.S. Appl. No. 17/525,327, filed Nov. 12, 2021, entitled Bragg Reflector for Photonic Chip Security Structure, 37 pages. [cited by applicant]
U.S. Appl. No. 17/525,293, filed Nov. 12, 2021, entitled Photonic Chip Security Structure, 24 pages. [cited by applicant]
Non Final Office Action mailed Jan. 29, 2025 for U.S. Appl. No. 17/932,868, filed Sep. 16, 2022; pp. 36. [cited by applicant]
Final Office Action mailed May 15, 2025 for U.S. Appl. No. 17/932,868, filed Sep. 16, 2022; p. 15. [cited by applicant]