Partial directional etch method and resulting structures
View Patent ↗In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.
1. A transistor comprising:
a fin extending from a substrate;
an dielectric material formed over the fin;
a metal gate, including a gate dielectric, within a trench in the dielectric material, the meta gate extending over a top and sidewalls of the fin; and
a dummy gate remnant extending along a bottom portion of the trench, the dummy gate remnant being interjacent the gate dielectric and the substrate and extending in a direction perpendicular to the major surface of the substrate.
2. The transistor of claim 1 , wherein the dummy gate remnant widens outwards from a nominal edge.
3. The transistor of claim 1 , wherein the dummy gate remnant extends from a first sidewall of the trench to a second sidewall of the trench.
4. The transistor of claim 1 , wherein the dummy gate remnant is confined to bottom corners of the trench.
5. The transistor of claim 1 , wherein the metal gate has a cross-section shape having a first portion having substantially vertical sidewalls and a footing portion wherein the sidewalls widen outwards.
6. The transistor of claim 1 , wherein the dummy gate remnant comprises polysilicon.
7. The transistor of claim 1 , wherein the dummy gate remnant comprises polysilicon and silicon oxide.
8. The transistor of claim 1 , further comprising a source/drain region at least partially within the fin.
9. The transistor of claim 8 , wherein the dummy gate remnant extends from a sidewall of the metal gate to a sidewall of the source/drain region, when viewed from a top-down perspective.
10. A transistor comprising:
a fin extending from a substrate;
a source/drain region extending from the fin;
a gate dielectric extending over the fin;
a multi-layer metal gate electrode extending over the gate dielectric, the multi-layer metal gate electrode including a cross-section shape having a first portion having substantially vertical sidewalls and a footing portion wherein the sidewalls widen outwards; and
a dummy gate remnant extending from a sidewall of the multi-layer metal gate electrode to a sidewall of the source/drain region, when viewed from a top-down perspective.
11. The transistor of claim 10 , wherein, from a top down perspective:
the fin has a major longitudinal axis extending in a first direction; and
the dummy gate remnant has a major longitudinal axis extending in a second direction, the second direction being substantially perpendicular to the first direction.
12. The transistor of claim 10 , wherein the dummy gate remnant comprises polysilicon.
13. The transistor of claim 10 , wherein the multi-layer metal gate electrode fills a trench of a dielectric material overlying the fin.
14. The transistor of claim 13 , wherein the dummy gate remnant is extends from a first sidewall of the trench to a second sidewall of the trench.
15. The transistor of claim 13 , wherein the dummy gate remnant is confined to bottom corners of the trench.
16. A method of forming a transistor, the method comprising:
forming a dummy gate over a substrate structure;
forming spacers on respective sidewalls of the dummy gate;
forming source region and a drain region, respectively, on opposing sides of the dummy gate;
depositing a dielectric layer to surround the dummy gate, the source region and the drain region;
isotropically etching the dummy gate to remove a top portion of the dummy gate and to leave a bottom portion of the dummy gate;
anisotropically etching the bottom portion of the dummy gate to partially remove the bottom portion of the dummy gate and to leave a remnant portion of the dummy gate; and
forming on the remnant portion, a metal gate, wherein the remnant portion extends from a sidewall of the metal gate electrode to a sidewall of the source region when viewed in top-down perspective.
17. The method of claim 16 , wherein the step of isotropically etching the dummy gate includes performing a wet etch or remote plasma etch.
18. The method of claim 16 , wherein the step of anisotropically etching the bottom portion of the dummy gate includes performing a plasma etch with ion bombardment to remove some but not all of the bottom portion while leaving the remnant portion of the dummy gate.
19. The method of claim 16 , wherein the steps of isotropically etching the dummy gate and of anisotropically etching the bottom portion of the dummy gate forms a trench in the dielectric layer and further wherein the remnant portion of the dummy gate remains at bottom corners of the trench.
20. The method of claim 16 , wherein the step of forming on the remnant portion a metal gate electrode includes forming a gate dielectric directly on the remnant portion.