Memory device and method of forming the same
A memory device includes a semiconductor substrate, an isolation structure, and an anti-fuse structure. The isolation structure is disposed in the semiconductor substrate. The anti-fuse structure is disposed in the isolation structure and includes a first electrode and a second electrode. The second electrode is disposed adjacent to the first electrode. Both of a top surface of the first electrode and a top surface of the second electrode are below a top surface of the semiconductor substrate.
1. A memory device, comprising:
a semiconductor substrate;
an isolation structure in the semiconductor substrate; and
an anti-fuse structure in the isolation structure, the anti-fuse structure comprising:
a first electrode; and
a second electrode adjacent to the first electrode, wherein both of a top surface of the first electrode and a top surface of the second electrode are below a top surface of the semiconductor substrate, wherein both of the top surface of the first electrode and the top surface of the second electrode are below a top surface of the isolation structure.
2. The memory device of claim 1 , further comprising:
a first contact on the first electrode; and
a second contact on the second electrode.
3. The memory device of claim 2 , wherein both of a bottom surface of the first contact and a bottom surface of the second contact are below the top surface of the semiconductor substrate.
4. The memory device of claim 2 , further comprising:
a dielectric layer above the semiconductor substrate and the isolation structure.
5. The memory device of claim 4 , wherein the first contact includes a bottom portion in the isolation structure and a top portion in the dielectric layer.
6. The memory device of claim 2 , wherein the first contact is configured to apply a first voltage to the first electrode and the second contact is configured to apply a second voltage different from the first voltage to the second electrode to convert a portion of the isolation structure between the first electrode and the second electrode into a permanent electrically conductive path.
7. The memory device of claim 1 , wherein the top surface of the first electrode is substantially coplanar with the top surface of the second electrode.
8. The memory device of claim 1 , wherein a bottom surface of the first electrode is substantially coplanar with a bottom surface of the second electrode.
9. The memory device of claim 1 , wherein the first electrode extends along a first direction, and the first electrode and the second electrode are arranged parallel with each other along a second direction perpendicular to the first direction in a top view.
10. The memory device of claim 1 , wherein the first electrode has a strip profile in a top view.
11. The memory device of claim 1 , wherein the first electrode and the second electrode comprise the same materials.
12. A method of forming memory device, comprising:
forming an isolation structure in a semiconductor substrate;
etching the isolation structure to form a first opening and a second opening;
forming a first electrode and a second electrode of an anti-fuse structure respectively in the first opening and the second opening such that both of a top surface of the first electrode and a top surface of the second electrode are below a top surface of the isolation structure;
forming a dielectric layer above the isolation structure; and
applying a first voltage to the first electrode and a second voltage different from the first voltage to the second electrode to convert a portion of the isolation structure between the first electrode and the second electrode into a permanent electrically conductive path.
13. The method of claim 12 , further comprising:
forming a first contact and a second contact in the dielectric layer such that the first voltage is applied to the first electrode through the first contact and the second voltage is applied to the second electrode through the second contact.
14. The method of claim 13 , wherein forming the first contact and the second contact is performed such that a portion of the first contact and a portion of the second contact are formed within the isolation structure.
15. The method of claim 13 , wherein forming the first contact and the second contact is performed such that the top surface of the first electrode and the top surface of the second electrode are respectively in contact with the first contact and the second contact.
16. The method of claim 12 , wherein forming the first electrode and the second electrode is performed further such that the top surface of the first electrode and the top surface the second electrode are below a top surface of the semiconductor substrate.
17. The method of claim 12 , wherein forming the first electrode and the second electrode is performed such that the first electrode and the second electrode are in contact with the isolation structure.
18. The method of claim 12 , wherein forming the first electrode and the second electrode is performed such that a bottom surface of the first electrode is coplanar with a bottom surface of the second electrode.
19. The method of claim 12 , wherein forming the isolation structure in the semiconductor substrate comprises:
forming a trench in the semiconductor substrate; and
filling an anti-fuse dielectric material in the trench to form the isolation structure.