Dual-port SRAM structure

1. A device structure, comprising:

a substrate comprising an n-well disposed between a first p-well and a second p-well along a first direction;

a first active region and a second active region disposed over the n-well and extending along a second direction perpendicular to the first direction;

a third active region and a fourth active region disposed over the first p-well and extending along the second direction;

a fifth active region and a sixth active region disposed over the second p-well and extending along the second direction;

a first gate structure extending along the first direction to wrap over the third active region, the fourth active region, and the first active region; and

a second gate structure extending along the first direction to wrap over the second active region, the fifth active region, and the sixth active region.

2. The device structure of claim 1 ,

wherein each of the first active region and the second active region comprises a single fin,

wherein each of the third active region, the fourth active region, the fifth active region, and the sixth active region comprises two fins.

3. The device structure of claim 1 ,

wherein the third active region and the fourth active region is spaced apart by a first spacing,

wherein the fourth active region and the first active region is spaced apart by a second spacing greater than the first spacing.

4. The device structure of claim 3 , wherein a ratio of the second spacing to the first spacing is between about 1.05 and about 2.00.

5. The device structure of claim 1 ,

wherein the third active region comprises a first source/drain region, a second source/drain region, a third source/drain region, a first channel region disposed between the first source/drain region and the second source/drain region, a second channel region disposed between the second source/drain region and the third source/drain region,

wherein the fourth active region comprises a first source/drain region, a second source/drain region, a third source/drain region, a first channel region disposed between the first source/drain region and the second source/drain region, a second channel region disposed between the second source/drain region and the third source/drain region,

wherein the first active region comprises a channel region disposed between a first source/drain region and a second source/drain region.

6. The device structure of claim 5 , wherein the first gate structure wraps over the first channel region of the third active region, the first channel region of the fourth active region, and the channel region of the first active region.

7. The device structure of claim 5 , further comprising:

a first long contact disposed over the second source/drain region of the third active region, the second source/drain region of the fourth active region, and the second source/drain region of the first active region.

8. The device structure of claim 7 , further comprising:

a second long contact disposed over the first source/drain region of the third active region and the first source/drain region of the fourth active region.

9. A device structure, comprising:

a substrate comprising an n-well disposed between a first p-well and a second p-well along a first direction;

a first active region and a second active region disposed over the n-well and extending along a second direction perpendicular to the first direction;

a third active region and a fourth active region disposed over the first p-well and extending along the second direction;

a fifth active region and a sixth active region disposed over the second p-well and extending along the second direction;

a first gate structure disposed over the third active region;

a second gate structure disposed over the fourth active region;

a third gate structure disposed over the fifth active region; and

a fourth gate structure disposed over the sixth active region,

wherein the first gate structure and the fourth gate structure are electrically coupled together by way of a first word line disposed in a first metal layer,

wherein the second gate structure and the fourth gate structure are electrically coupled together by way of a second word line disposed in a second metal layer different from the first metal layer.

10. The device structure of claim 9 , wherein the first metal layer is disposed over the second metal layer.

11. The device structure of claim 9 ,

wherein the first word line and the second word line extend lengthwise along a first direction,

wherein the first word line comprises a first width along a second direction perpendicular to the first direction,

wherein the second word line comprises a second width along the second direction,

wherein the first width is greater than the second width.

12. The device structure of claim 11 , wherein a section of the second word line comprises a metal jog feature to increase the second width of the section of the second word line.

13. The device structure of claim 11 ,

wherein the first gate structure and the second gate structure are aligned along the first direction,

wherein the third gate structure and the fourth gate structure are aligned along the first direction.

14. The device structure of claim 13 , further comprising:

a first common gate structure wrapping over the first active region, the second active region and the third active region; and

a second common gate structure wrapping over the fourth active region, the fifth active region and the sixth active region,

wherein the first common gate structure extends parallel to the first gate structure and the second gate structure,

wherein the second common gate structure extends parallel to the third gate structure and the fourth gate structure.

15. The device structure of claim 14 ,

wherein the first common gate structure is aligned with the third gate structure and the fourth gate structure along the first direction,

wherein the second common gate structure is aligned with the first gate structure and the second gate structure along the first direction.

16. A static random access memory (SRAM) cell comprising:

a first pull-down device (PD- 1 ), a second pull-down device (PD- 2 ), a first pass-gate device (PG- 1 ), and a second pass-gate device (PG- 2 ) disposed in a first p-well on a substrate, wherein the first pass-gate device (PG- 1 ) and the first pull-down device (PD- 1 ) share a first active region extending along a first direction, wherein the second pass-gate device (PG- 2 ) and the second pull-down device (PD- 2 ) share a second active region extending along the first direction;

a third pull-down device (PD- 3 ), a fourth pull-down device (PD- 4 ), a third pass-gate device (PG- 3 ), and a fourth pass-gate device (PG- 4 ) disposed in a second p-well on the substrate; and

a first pull-up device (PU- 1 ) and a second pull-up device (PU- 2 ) disposed in an n-well disposed between the first p-well and the second p-well, where a third active region of the first pull-up device (PU- 1 ) extends along the first direction,

wherein a drain of the first pull-down device (PD- 1 ), a drain of the second pull-down device (PD- 2 ), and a drain the first pull-up device (PU- 1 ) are electrically coupled together by way of a first long contact,

wherein a source of the first pull-down device (PD- 1 ) and a source of the second pull-down device (PD- 2 ) are electrically coupled together by way of a second long contact.

17. The SRAM cell of claim 16 ,

wherein the first active region and the second active region are spaced apart by a first spacing,

wherein the second active region and the third active region are spaced apart by a second spacing greater than the first spacing.

18. The SRAM cell of claim 17 , wherein a ratio of the second spacing to the first spacing is between 1.05 and 2.

19. The SRAM cell of claim 16 ,

wherein the first active region comprises two fin structures,

wherein the second active region comprises two fin structures,

wherein the third active region comprises a single fin structure.

20. The SRAM cell of claim 16 , wherein the first pull-down device (PD- 1 ), the second pull-down device (PD- 2 ), and the first pull-up device (PU- 1 ) share a common gate structure.