Two-port SRAM cell structure
View Patent ↗A circuit includes a Vdd node, and a two-port Static Random-Access Memory (SRAM) cell pair having a first SRAM cell and a second SRAM cell having a same structure. The first SRAM cell is a ten-transistor SRAM cell that comprises a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming a latch with the first pull-up transistor and the second pull-up transistor, a first pass-gate transistor and a second pass-gate transistor connecting to the latch, a p-type isolation transistor including a first source/drain region connecting to a drain region of the first pull-up transistor, and a gate connecting to the Vdd node. The circuit further includes a read bit-line shared with the second SRAM cell. and a write bit-line pair connecting to gates of the first pass-gate transistor and the second pass-gate transistor.
1 . A circuit comprising:
a two-port Static Random-Access Memory (SRAM) cell pair comprising:
a first two-port SRAM cell comprising:
a first pull-up transistor and a second pull-up transistor forming parts of a latch;
a first pass-gate transistor and a second pass-gate transistor connecting to the first pull-up transistor and the second pull-up transistor, respectively;
a first node-decoupling structure and a second node-decoupling structure connecting to drains of the first pull-up transistor and the second pull-up transistor, respectively;
a first pair of write bit-lines configured to write into the first two-port SRAM cell; and
a first part of a read bit-line parallel to, and on a side of, the first pair of write bit-lines; and
a second two-port SRAM cell abutting the first two-port SRAM cell, wherein the second SRAM cell comprises:
a second pair of write bit-lines; and
a second part of the read bit-line parallel to, and on a side of, the second pair of write bit-lines.
2 . The circuit of claim 1 , wherein a middle line of the read bit-line passes through middle of each of the first part and the second part of the read bit-line.
3 . The circuit of claim 1 , wherein each of the first two-port SRAM cell and the second two-port SRAM cell occupies an L-shaped chip area.
4 . The circuit of claim 3 , wherein the first two-port SRAM cell and the second two-port SRAM cell fit to each other to occupy a rectangular chip area.
5 . The circuit of claim 3 , wherein an inner boundary between the first two-port SRAM cell and the second two-port SRAM cell comprises:
a first section; and
a second section and a third section connecting to opposite ends of the first section, wherein the second section and the third section are perpendicular to the first section.
6 . The circuit of claim 1 , wherein the first node-decoupling structure comprises an isolation transistor that is constantly turned off.
7 . The circuit of claim 6 , wherein the first two-port SRAM cell is a 10-transistor SRAM cell.
8 . The circuit of claim 1 , wherein the first node-decoupling structure comprises a dielectric gate, and a first semiconductor region and a second semiconductor region on opposing sides of the dielectric gate.
9 . The circuit of claim 8 , wherein the first two-port SRAM cell is an 8-transistor SRAM cell.
10 . The circuit of claim 1 , wherein the two-port SRAM cell pair comprises five elongated active regions, wherein first two of the elongated active regions are in the first two-port SRAM cell, the second two of the elongated active regions are in the second two-port SRAM cell, and wherein a fifth elongated active region is shared by the first two-port SRAM cell and the second two-port SRAM cell.
11 . The circuit of claim 1 , wherein the first two-port SRAM cell comprises:
a Vss node; and
a read pull-down transistor and a read pass-gate transistor, wherein the read pull-down transistor is connected between the Vss node and the read pass-gate transistor, and the read pass-gate transistor is between the read pull-down transistor and the read bit-line.
12 . The circuit of claim 1 , wherein the first two-port SRAM cell comprises:
a Vss node; and
a read pull-down transistor and a read pass-gate transistor, wherein the read pull-down transistor is connected between the read bit-line and the read pass-gate transistor, and the read pass-gate transistor is between the read pull-down transistor and the Vss node.
13 . A circuit comprising:
a Vdd node; and
a two-port Static Random-Access Memory (SRAM) cell pair comprising a first SRAM cell and a second SRAM cell having a same structure, wherein the first SRAM cell is a ten-transistor SRAM cell comprising:
a first pull-up transistor and a second pull-up transistor;
a first pull-down transistor and a second pull-down transistor forming a latch with the first pull-up transistor and the second pull-up transistor;
a first pass-gate transistor and a second pass-gate transistor connecting to the latch;
a p-type isolation transistor comprising a first source/drain region connecting to a drain region of the first pull-up transistor, and a gate connecting to the Vdd node;
a read bit-line shared with the second SRAM cell; and
a write bit-line pair connecting to gates of the first pass-gate transistor and the second pass-gate transistor.
14 . The circuit of claim 13 , wherein the p-type isolation transistor further comprises a second source/drain region connecting to an additional drain region of an additional pull-up transistor in a third SRAM cell.
15 . The circuit of claim 13 , wherein the read bit-line is located in a bottommost metal layer (M 1 ) of a respective die, and wherein the write bit-line pair is located in a M 2 metal layer over the bottommost metal layer.
16 . The circuit of claim 15 , wherein a first lengthwise direction of the read bit-line is parallel to a second lengthwise direction of the write bit-line pair.
17 . The circuit of claim 13 , wherein the read bit-line comprises a first part in the first SRAM cell and a second part in the second SRAM cell, and wherein a first middle line of the first part and a second middle line of the second part are aligned to a same straight line.
18 . A circuit comprising:
a Vdd node; and
a two-port Static Random-Access Memory (SRAM) cell pair comprising a first SRAM cell and a second SRAM cell having a same structure, wherein the first SRAM cell is a ten-transistor SRAM cell comprising:
a first pull-up transistor and a second pull-up transistor;
a first pull-down transistor and a second pull-down transistor forming a latch with the first pull-up transistor and the second pull-up transistor;
a first pass-gate transistor and a second pass-gate transistor connecting to the latch;
a node-decoupling structure comprising:
a gate structure; and
a first semiconductor region and a second semiconductor region on opposing sides of the gate structure, wherein the first semiconductor region is connected to a drain region of the first pull-up transistor, and wherein the node-decoupling structure is configured to electrically decouple the first semiconductor region from the second semiconductor region;
a read bit-line shared with the second SRAM cell; and
a write bit-line pair connecting to the first pass-gate transistor and the second pass-gate transistor.
19 . The circuit of claim 18 , wherein the node-decoupling structure comprises an isolation transistor, and the isolation transistor comprises the gate structure as a gate, and the first semiconductor region and the second semiconductor region as source and drain regions, and wherein the isolation transistor is configured to be turned off constantly.
20 . The circuit of claim 18 , wherein the gate structure comprises a dielectric gate.